Patents by Inventor Alan Welsh Sinclair
Alan Welsh Sinclair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7340581Abstract: According to a first aspect of the invention, there is provided a controller connected to a non-volatile memory and including a volatile memory, wherein the controller maintains lists in volatile memory of blocks in the non-volatile memory allocated for storage of logical sector data and of blocks recently erased in the non-volatile memory.Type: GrantFiled: September 27, 2002Date of Patent: March 4, 2008Assignee: Lexar Media, Inc.Inventors: Sergey Anatolievich Gorobets, Alan David Bennett, Alan Welsh Sinclair
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Patent number: 7310699Abstract: A data storage device is provided. A disk device is combined with a non-volatile memory device to provide much shorter write access time and much higher data write speed than can be achieved with a disk device alone. Interleaving bursts of sector writes between the two storage devices can effectively eliminate the effect of the seek time of the disk device. Following a non-contiguous logical address transition from a host system, the storage controller can perform a look-ahead seek operation on the disk device, while writing current data to the non-volatile memory device. Such a system can exploit the inherently faster write access characteristics of a non-volatile memory device, eliminating the dead time normally caused by the disk seek time.Type: GrantFiled: September 29, 2006Date of Patent: December 18, 2007Assignee: SanDisk CorporationInventor: Alan Welsh Sinclair
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Patent number: 7302534Abstract: A dual media storage device is provided. Two separate non-volatile mass storage devices, one having a faster access time and a lower capacity than the other, are combined into a single system. A storage controller can direct the flow of data into one device or the other, depending upon various conditions, which might include one mass storage device being unavailable or for certain caching schemes.Type: GrantFiled: September 29, 2006Date of Patent: November 27, 2007Assignee: SanDisk CorporationInventor: Alan Welsh Sinclair
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Patent number: 7139864Abstract: A non-volatile memory system is organized in physical groups of physical memory locations. Each physical group (metablock) is erasable as a unit and can be used to store a logical group of data. A memory management system allows for update of a logical group of data by allocating a metablock dedicated to recording the update data of the logical group. The update metablock records update data in the order received and has no restriction on whether the recording is in the correct logical order as originally stored (sequential) or not (chaotic). Eventually the update metablock is closed to further recording. One of several processes will take place, but will ultimately end up with a fully filled metablock in the correct order which replaces the original metablock. In the chaotic case, directory data is maintained in the non-volatile memory in a manner that is conducive to frequent updates. The system supports multiple logical groups being updated concurrently.Type: GrantFiled: December 30, 2003Date of Patent: November 21, 2006Assignee: SanDisk CorporationInventors: Alan David Bennett, Alan Douglas Bryce, Sergey Gorobets, Alan Welsh Sinclair, Peter John Smith
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Patent number: 7136973Abstract: A dual media storage device is provided. Two separate non-volatile mass storage devices, one having a faster access time and a lower capacity than the other, are combined into a single system. A storage controller can direct the flow of data into one device or the other, depending upon various conditions, which might include one mass storage device being unavailable or for certain caching schemes.Type: GrantFiled: February 4, 2004Date of Patent: November 14, 2006Assignee: SanDisk CorporationInventor: Alan Welsh Sinclair
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Patent number: 7127549Abstract: A data storage device is provided. A disk device is combined with a non-volatile memory device to provide much shorter write access time and much higher data write speed than can be achieved with a disk device alone. Interleaving bursts of sector writes between the two storage devices can effectively eliminate the effect of the seek time of the disk device. Following a non-contiguous logical address transition from a host system, the storage controller can perform a look-ahead seek operation on the disk device, while writing current data to the non-volatile memory device. Such a system can exploit the inherently faster write access characteristics of a non-volatile memory device, eliminating the dead time normally caused by the disk seek time.Type: GrantFiled: February 4, 2004Date of Patent: October 24, 2006Assignee: SanDisk CorporationInventor: Alan Welsh Sinclair
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Patent number: 6813678Abstract: A memory system (10) comprising a non-volatile memory (18) having memory locations (38), and a controller (16) for writing data structures to and reading data structures from the memory. The system (10) is architecturally configured so that the locations (38) can be written to individually but are erasable only in blocks. The controller (16) forms one or more erasable units (39) which are each subdivided into cells (50) each consisting of a group of locations (38). The controller (16) writes data structures to and reads structures from each cell (50) on a per cell basis. The system (10) may comprise a controller (16) embedded in a FLASH memory card. Alternatively, the controller (16) may be embedded in, or implemented in, a host system such as a Personal Computer (PC).Type: GrantFiled: September 6, 2000Date of Patent: November 2, 2004Assignee: Lexar Media, Inc.Inventors: Alan Welsh Sinclair, Sergei Anatolovich Gorobets
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Patent number: 6725321Abstract: A memory system (10) having a solid state memory (6) comprising non-volatile individually addressable memory sectors (1) arranged in erasable blocks, and a controller (8) for writing to reading from the sectors, and for sorting the blocks into “erased” and “not erased” blocks. The controller performs logical to physical address translation, and includes a Write Pointer (WP) for pointing to the physical sector address to which data is to be written from a host processor. A Sector Allocation Table (SAT) of logical adrresses with respective physical addresses is stored in the memory, and the controller updates the SAT less frequently than sectors are written to with data from the host processor. The memory may be in a single chip, or in a plurality of chips. A novel system for arranging data in the individual sectors (1) is also claimed.Type: GrantFiled: March 1, 2001Date of Patent: April 20, 2004Assignee: Lexar Media, Inc.Inventors: Alan Welsh Sinclair, Natalia Victorovna Ouspenskaia, Richard Michael Taylor, Sergey Anatolievich Gorobets
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Patent number: 6711059Abstract: According to a first aspect of the present invention, there is provided a memory system having a controller and a non-volatile memory storing firmware for start up and for normal operation of the system, the controller comprising, a volatile memory; and a processor; wherein the controller is arranged to operate during initialization or configuration of the system so that the start up firmware stored in the non-volatile memory is loaded into the volatile memory under hardware control by the controller and with the processor halted, the start up firmware in the volatile memory being subsequently executed by the processor.Type: GrantFiled: September 27, 2002Date of Patent: March 23, 2004Assignee: Lexar Media, Inc.Inventors: Alan Welsh Sinclair, Peter John Smith, Robert Edwin Payne
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Publication number: 20030165076Abstract: According to a first aspect of the invention, there is provided a controller connected to a non-volatile memory and including a volatile memory, wherein the controller maintains lists in volatile memory of blocks in the non-volatile memory allocated for storage of logical sector data and of blocks recently erased in the non- volatile memory.Type: ApplicationFiled: September 27, 2002Publication date: September 4, 2003Inventors: Sergey Anatolievich Gorobets, Alan David Bennett, Alan Welsh Sinclair
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Publication number: 20030156473Abstract: According to a first aspect of the present invention, there is provided a memory system having a controller and a non-volatile memory storing firmware for start up and for normal operation of the system, the controller comprising, a volatile memory; and a processor; wherein the controller is arranged to operate during initialization or configuration of the system so that the start up firmware stored in the non-volatile memory is loaded into the volatile memory under hardware control by the controller and with the processor halted, the start up firmware in the volatile memory being subsequently executed by the processor.Type: ApplicationFiled: September 27, 2002Publication date: August 21, 2003Inventors: Alan Welsh Sinclair, Peter John Smith, Robert Edwin Payne
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Patent number: 6578127Abstract: A computer system has a memory device. The memory device includes a user interface, a controller, a store, and an address mapping device for mapping a first address from the user interface to a second address for accessing the store, where the controller stores information in successive regions of the store each time the information is updated.Type: GrantFiled: October 1, 1998Date of Patent: June 10, 2003Assignee: Lexar Media, Inc.Inventor: Alan Welsh Sinclair
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Patent number: 6490649Abstract: An addressable memory device for storing blocks of varying length, utilizes a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.Type: GrantFiled: February 28, 2002Date of Patent: December 3, 2002Assignee: Lexar Media, Inc.Inventor: Alan Welsh Sinclair
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Patent number: 6467021Abstract: A data system comprising a store (10), a memory (12), a user interface (32) and a memory controller (24) where the memory is used to buffer all data transferred between the user interface and the store, the system being characterized in that the memory controller copies data directly between the store and the memory, whereas the memory controller re-organizes data when the data is transferred between the memory and the user interface.Type: GrantFiled: October 1, 1998Date of Patent: October 15, 2002Assignee: Memquest, Inc.Inventor: Alan Welsh Sinclair
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Publication number: 20020103960Abstract: An addressable memory device for storing blocks of varying length, utilises a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.Type: ApplicationFiled: February 28, 2002Publication date: August 1, 2002Inventor: Alan Welsh Sinclair
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Patent number: 6345367Abstract: A fault tolerant memory system includes an array of block-erasable storage elements (12). Each block (12) of storage locations is sub-divided into sub-groups (14) of storage elements. A control information store means holds defect information for each group in each block and an address counter holds the addresses of the groups in the particular erase block being erased. A testing circuit checks whether the defect information stored in the control information store for the particular group currently addressed by the address counter indicates that the particular group contains one or more defective storage locations. If it does it increments the address counter.Type: GrantFiled: February 16, 1999Date of Patent: February 5, 2002Assignee: Memory Corporation PLCInventor: Alan Welsh Sinclair
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Patent number: 6285607Abstract: A memory system (10) incorporating a plurality of memory devices (42) at least one of which has a defective location. Defects are mapped in a non-volatile memory (46). Data structures are divided into portions which are respectively stored in different ones of the memory devices (42). The controller (17) of the system accesses the non-volatile memory so as to generate on a per device basis an address corresponding to a non-defective location in that device. In this system, different addresses may therefore be applied to different ones of the devices (42) when a data structure is written to or read from the memory devices.Type: GrantFiled: October 20, 2000Date of Patent: September 4, 2001Assignee: Memory Corporation PLCInventor: Alan Welsh Sinclair
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Publication number: 20010011334Abstract: An addressable memory device for storing blocks of varying length, utilises a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.Type: ApplicationFiled: November 10, 1998Publication date: August 2, 2001Inventor: ALAN WELSH SINCLAIR
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Patent number: 6069827Abstract: A solid state memory for emulating a disk drive comprising: translation means for translating a logical sector address to a main memory address; a main memory composed of non-volatile memory cells erasable in blocks; characterized in that a first pointer is used to point to an unwritten location in main memory, and a second pointer is used to point to the next unerased erasable block in sequence to the erasable block containing the said unwritten memory location; control means being provided to ensure that there is always at least one erasable block in the erased condition between the first and second pointers.Type: GrantFiled: March 24, 1998Date of Patent: May 30, 2000Assignee: Memory Corporation PLCInventor: Alan Welsh Sinclair
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Patent number: 3993918Abstract: A master/slave bistable arrangement which operates on current levels rather than voltage levels and with a single input of clock pulses. There are different bias current levels which are advantageously supplied by multi-layer current injection structures in integrated form.Type: GrantFiled: December 12, 1974Date of Patent: November 23, 1976Assignee: U.S. Philips CorporationInventor: Alan Welsh Sinclair