Patents by Inventor Alan Xuguang Wang
Alan Xuguang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8966181Abstract: Various embodiments of the present invention are generally directed to an apparatus and method for non-volatile caching of data in a memory hierarchy of a data storage device. In accordance with some embodiments, a pipeline memory structure is provided to store data for use by a controller. The pipeline has a plurality of hierarchical cache levels each with an associated non-volatile filter cache and a non-volatile victim cache. Data retrieved from each cache level are respectively promoted to the associated non-volatile filter cache. Data replaced in each cache level are respectively demoted to the associated non-volatile victim cache.Type: GrantFiled: December 11, 2008Date of Patent: February 24, 2015Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Alan Xuguang Wang
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Patent number: 8553454Abstract: Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.Type: GrantFiled: February 20, 2012Date of Patent: October 8, 2013Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
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Patent number: 8526252Abstract: A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a column decoder connected to the plurality of unit cells. A test circuitry sends a non-operational test pattern through the array via the row and column decoders with a quiescent supply current to identify defects in the array of memory cells.Type: GrantFiled: March 17, 2009Date of Patent: September 3, 2013Assignee: Seagate Technology LLCInventors: Hai Li, Yiran Chen, Alan Xuguang Wang, Haiwen Xi, Wenzhong Zhu, Andreas K. Roelofs
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Patent number: 8320169Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.Type: GrantFiled: December 21, 2011Date of Patent: November 27, 2012Assignee: Seagate Technology LLCInventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
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Publication number: 20120147665Abstract: Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.Type: ApplicationFiled: February 20, 2012Publication date: June 14, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
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Publication number: 20120087175Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.Type: ApplicationFiled: December 21, 2011Publication date: April 12, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
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Patent number: 8154914Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.Type: GrantFiled: January 28, 2011Date of Patent: April 10, 2012Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
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Patent number: 8107282Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.Type: GrantFiled: January 28, 2011Date of Patent: January 31, 2012Assignee: Seagate Technology LLCInventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
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Patent number: 8054678Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.Type: GrantFiled: October 7, 2010Date of Patent: November 8, 2011Assignee: Seagate Technology LLCInventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
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Patent number: 8004875Abstract: A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines.Type: GrantFiled: July 13, 2009Date of Patent: August 23, 2011Assignee: Seagate Technology LLCInventors: Markus Jan Peter Siegert, Michael Xuefei Tang, Andrew John Carter, Alan Xuguang Wang
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Publication number: 20110134688Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.Type: ApplicationFiled: January 28, 2011Publication date: June 9, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
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Publication number: 20110128778Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.Type: ApplicationFiled: January 28, 2011Publication date: June 2, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
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Patent number: 7916528Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.Type: GrantFiled: March 30, 2009Date of Patent: March 29, 2011Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
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Patent number: 7916515Abstract: An apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell. In some embodiments, a control circuitry is configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense element.Type: GrantFiled: March 10, 2009Date of Patent: March 29, 2011Assignee: Seagate Technology LLCInventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Alan Xuguang Wang
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Patent number: 7894250Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.Type: GrantFiled: March 17, 2009Date of Patent: February 22, 2011Assignee: Seagate Technology LLCInventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
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Patent number: 7881096Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.Type: GrantFiled: March 23, 2009Date of Patent: February 1, 2011Assignee: Seagate Technology LLCInventors: Wenzhong Zhu, Yong Lu, Xiaobin Wang, Yiran Chen, Alan Xuguang Wang, Xiaohua Lou, Haiwen Xi
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Publication number: 20110019466Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.Type: ApplicationFiled: October 7, 2010Publication date: January 27, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
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Publication number: 20110007550Abstract: A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: Seagate Technology LLCInventors: Markus Jan Peter Siegert, Michael Xuefei Tang, Andrew John Carter, Alan Xuguang Wang
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Publication number: 20100246251Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.Type: ApplicationFiled: March 30, 2009Publication date: September 30, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
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Publication number: 20100238700Abstract: A method and apparatus for testing an array of non-volatile memory cells, such as a spin-torque transfer random access memory (STRAM). In some embodiments, an array of memory cells having a plurality of unit cells with a resistive sense element and a switching device has a row decoder and a column decoder connected to the plurality of unit cells. A test circuitry sends a non-operational test pattern through the array via the row and column decoders with a quiescent supply current to identify defects in the array of memory cells.Type: ApplicationFiled: March 17, 2009Publication date: September 23, 2010Applicant: SEAGATE TECHNOLOGY LLCInventors: Hai Li, Yiran Chen, Alan Xuguang Wang, Haiwen Xi, Wenzhong Zhu, Andreas K. Roelofs