Abstract: A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.

Abstract: Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Abstract: Embodiments of the present invention provide a method and apparatus for handling memory refresh and maintenance operations for graphics and other applications. In particular, refresh and memory operations are executed in two stages. A first stage includes, but is not limited to, memory channel temperature calibration, RAC auto current calibration, and RAC auto temperature calibration. First stage operations are scheduled when the primary display is not requesting data from memory, such as when the display is in its vertical blanking interval. A second stage includes, but is not limited to, memory refreshes and memory current calibration. These operations are scheduled when there are no display streams (primary and secondary) or when display is requesting in a low priority mode.

Abstract: According to one aspect of the invention, a method is provided in which a first clock signal is generated. A second clock signal is derived from the first clock signal. The second clock signal is delayed relative to the first clock signal by a first delay period by a delay locked loop (DLL) circuit. The second clock signal is used to latch incoming data from a memory device.

Abstract: According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Abstract: According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Abstract: Embodiments of the present invention provide a method and apparatus for handling memory refresh and maintenance operations for graphics and other applications. In particular, refresh and memory operations are executed in two stages. A first stage includes, but is not limited to, memory channel temperature calibration, RAC auto current calibration, and RAC auto temperature calibration. First stage operations are scheduled when the primary display is not requesting data from memory, such as when the display is in its vertical blanking interval. A second stage includes, but is not limited to, memory refreshes and memory current calibration. These operations are scheduled when there are no display streams (primary and secondary) or when display is requesting in a low priority mode.

Abstract: A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a status of the rows in an active mode.

Abstract: According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Abstract: Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Abstract: A graphics device implemented in accordance with one embodiment of the invention includes a first request path to a local memory interface for low-priority read transactions and a second request path to the local memory interface for low-priority write transactions. The second request path is also used for read transactions received over a system bus. The graphics device further includes an arbiter that arbitrates between the first request path and the second request path, with the second request path having a higher priority than the first request path.