Patents by Inventor Alastair BOOMER

Alastair BOOMER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low power bidirectional bus
    Patent number: 10218535
    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: February 26, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Willem Zwart, John Bruce Bowlerwell, Michael Page, Alastair Boomer
  • LOW POWER BIDIRECTIONAL BUS
    Publication number: 20180176034
    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
    Type: Application
    Filed: February 19, 2018
    Publication date: June 21, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Willem ZWART, John Bruce BOWLERWELL, Michael PAGE, Alastair BOOMER
  • Low power bidirectional bus
    Patent number: 9935786
    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 3, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Willem Zwart, John Bruce Bowlerwell, Michael Page, Alastair Boomer
  • LOW POWER BIDIRECTIONAL BUS
    Publication number: 20160269193
    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 15, 2016
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Willem ZWART, John Bruce BOWLERWELL, Michael PAGE, Alastair BOOMER