Patents by Inventor Alban Zaka
Alban Zaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984503Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a bulk substrate having an upper surface, a semiconductor layer above the bulk substrate, an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region on the bulk substrate, the source region and the drain region are raised above the upper surface of the bulk substrate, in which the source region and the drain region include an epitaxial semiconductor material, a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer, and a gate electrode above the gate dielectric.Type: GrantFiled: November 3, 2022Date of Patent: May 14, 2024Assignee: GlobalFoundries Dresden Module One LLC &Co. KGInventors: Ruchil Kumar Jain, Alban Zaka
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Publication number: 20240096868Abstract: Structures for a silicon-controlled rectifier and methods of forming same. The structure comprises a first well, a second well, and a third well in a semiconductor substrate. The third well is positioned between the first well and the second well. A first terminal includes a first doped region in the first well, and a second terminal includes a second doped region in the second well. The first well, the second well, and the second doped region have a first conductivity type, and the third well and the first doped region have a second conductivity type opposite to the first conductivity type. The structure further comprises a third doped region in the third well. The third doped region includes a first segment and a second segment, and the first segment is separated from the second segment by a portion of the first well and a portion of the third well.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Ajay, Ruchil Kumar Jain, Prantik Mahajan, Alban Zaka
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Patent number: 11929433Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.Type: GrantFiled: November 10, 2021Date of Patent: March 12, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Ignasi Cortes, Alban Zaka, Tom Herrmann, El Mehdi Bazizi, Richard Francis Taylor, III
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Publication number: 20240055434Abstract: A structure including a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer. The structure further includes a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer. The second FET has a source and a drain over the buried insulator layer. The structure further includes a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventors: Tom Herrmann, Zhixing Zhao, Alban Zaka, Yiching Chen
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Patent number: 11837605Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.Type: GrantFiled: December 17, 2021Date of Patent: December 5, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Tom Herrmann, Zhixing Zhao, Alban Zaka, Yiching Chen
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Publication number: 20230197731Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: Tom Herrmann, Zhixing Zhao, Alban Zaka, Yiching Chen
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Publication number: 20230115000Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a bulk substrate having an upper surface, a semiconductor layer above the bulk substrate, an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region on the bulk substrate, the source region and the drain region are raised above the upper surface of the bulk substrate, in which the source region and the drain region include an epitaxial semiconductor material, a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer, and a gate electrode above the gate dielectric.Type: ApplicationFiled: November 3, 2022Publication date: April 13, 2023Inventors: RUCHIL KUMAR JAIN, ALBAN ZAKA
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Patent number: 11610999Abstract: The present disclosure relates to semiconductor structures and, more particularly, to floating-gate devices and methods of manufacture. The structure includes: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor over and in electrical connection to the gate electrode.Type: GrantFiled: June 10, 2020Date of Patent: March 21, 2023Assignee: GLOBALFOUNDRIES DRESDEN MODULE ONE LIMITED LIABILITY COMPANY & CO. KGInventors: Alban Zaka, Tom Herrmann, Frank Schlaphof, Nan Wu
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Patent number: 11552192Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a bulk substrate, a semiconductor layer above the bulk substrate, an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region on the bulk substrate, a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer, and a gate electrode above the gate dielectric.Type: GrantFiled: May 17, 2020Date of Patent: January 10, 2023Assignee: GLOBALFOUNDRIES DRESDEN MODULE ONE LLC & CO. KGInventors: Ruchil Kumar Jain, Alban Zaka
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Patent number: 11315949Abstract: Disclosed are a semiconductor structure, which includes a charge-trapping sidewall spacer-type non-volatile memory (CTSS-NVM) device, and a method of forming the structure. The CTSS-NVM device includes asymmetric first and second sidewall spacers on opposing sidewalls of a gate structure above a channel region in a semiconductor substrate. The second sidewall spacer is wider than the first and includes multiple dielectric spacer layers, one of which is made of a charge-trapping material, is separated from the substrate (e.g., by a thin oxide layer), and has a bottom end closest to the substrate with a maximum width that is sufficient to achieve charge-trapping for proper CTSS-NVM device operation. The CTSS-NVM device further includes an epitaxial semiconductor layer for a source/drain region on the semiconductor substrate adjacent to the first sidewall spacer and a metal silicide layer for a Schottky barrier on the semiconductor substrate adjacent to the second sidewall spacer.Type: GrantFiled: September 15, 2020Date of Patent: April 26, 2022Assignee: GlobalFoundries Dresden Module One Limited Liability Company & Co. KGInventors: Tom Herrmann, Steven R. Soss, Leitao Liu, Alban Zaka
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Publication number: 20220085054Abstract: Disclosed are a semiconductor structure, which includes a charge-trapping sidewall spacer-type non-volatile memory (CTSS-NVM) device, and a method of forming the structure. The CTSS-NVM device includes asymmetric first and second sidewall spacers on opposing sidewalls of a gate structure above a channel region in a semiconductor substrate. The second sidewall spacer is wider than the first and includes multiple dielectric spacer layers, one of which is made of a charge-trapping material, is separated from the substrate (e.g., by a thin oxide layer), and has a bottom end closest to the substrate with a maximum width that is sufficient to achieve charge-trapping for proper CTSS-NVM device operation. The CTSS-NVM device further includes an epitaxial semiconductor layer for a source/drain region on the semiconductor substrate adjacent to the first sidewall spacer and a metal silicide layer for a Schottky barrier on the semiconductor substrate adjacent to the second sidewall spacer.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Applicant: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KGInventors: Tom Herrmann, Steven R. Soss, Leitao Liu, Alban Zaka
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Publication number: 20220069125Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Inventors: IGNASI CORTES, ALBAN ZAKA, TOM HERRMANN, EL MEHDI BAZIZI, RICHARD FRANCIS TAYLOR, III
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Patent number: 11245032Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.Type: GrantFiled: April 2, 2019Date of Patent: February 8, 2022Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Ignasi Cortes, Alban Zaka, Tom Herrmann, El Mehdi Bazizi, Richard Francis Taylor, III
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Publication number: 20210391457Abstract: The present disclosure relates to semiconductor structures and, more particularly, to floating-gate devices and methods of manufacture. The structure includes: a gate structure comprising a gate dielectric material and a gate electrode; and a vertically stacked capacitor over and in electrical connection to the gate electrode.Type: ApplicationFiled: June 10, 2020Publication date: December 16, 2021Inventors: Alban ZAKA, Tom HERRMANN, Frank SCHLAPHOF, Nan WU
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Publication number: 20210359130Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.Type: ApplicationFiled: May 17, 2020Publication date: November 18, 2021Inventors: RUCHIL KUMAR JAIN, ALBAN ZAKA
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Patent number: 10930777Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.Type: GrantFiled: November 21, 2017Date of Patent: February 23, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Ignasi Cortes Mayol, Alban Zaka, Tom Herrmann, El Mehdi Bazizi
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Publication number: 20200321466Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.Type: ApplicationFiled: April 2, 2019Publication date: October 8, 2020Inventors: IGNASI CORTES, ALBAN ZAKA, TOM HERRMANN, EL MEHDI BAZIZI, RICHARD FRANCIS TAYLOR III
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Patent number: 10644152Abstract: One illustrative integrated circuit product disclosed herein includes at least one transistor formed on an active region of on an SOI substrate, the transistor comprising a gate that includes a gate structure, first and second source/drain regions positioned on opposite sides of the gate, the first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type, and a doped region positioned below the gate, wherein the doped region has a lateral width that is at least substantially equal to the CPP (contact-poly-pitch) dimension of the transistor and is doped with a dopant material of the first type, wherein a first portion of the doped region is positioned vertically above an interface between the active region and a buried insulation layer of the SOI substrate and a second portion of the doped region is positioned vertically below the interface.Type: GrantFiled: January 28, 2019Date of Patent: May 5, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Alban Zaka, Luca Pirro, Tom Herrmann, El Mehdi Bazizi, Jan Hoentschel
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Patent number: 10580863Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.Type: GrantFiled: October 10, 2017Date of Patent: March 3, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Jan Hoentschel, Lars Mueller-Meskamp, Martin Gerhardt
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Patent number: 10497803Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully depleted silicon on insulator (SOI) semiconductor structures and methods of manufacture. The structure includes: a gate structure formed over a semiconductor material; a source region adjacent to the gate structure; a drain region remote from the gate structure; and a drift region separating the gate structure from the drain region. The drift region includes an epitaxial material grown on the semiconductor material which increases the thickness of the semiconductor material in the drift region.Type: GrantFiled: August 8, 2017Date of Patent: December 3, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ignasi Cortes Mayol, Christian Schippel, Alban Zaka, Tom Herrmann, El Mehdi Bazizi