Abstract: Described herein is a ruggedized microelectromechanical (“MEMS”) force sensor. The sensor employs piezoresistive or piezoelectric sensing elements for force sensing where the force is converted to strain and converted to electrical signal. In one aspect, both the piezoresistive and the piezoelectric sensing elements are formed on one substrate and later bonded to another substrate on which the integrated circuitry is formed. In another aspect, the piezoelectric sensing element is formed on one substrate and later bonded to another substrate on which both the piezoresistive sensing element and the integrated circuitry are formed.

Abstract: Integrated systems for force or strain sensing and haptic feedback are described herein. An example force-haptic system can include a sensor chip configured to receive an applied force, where the sensor chip includes at least one sensing element and an integrated circuit. The force-haptic system can also include a haptic actuator configured to convert an electrical excitation signal into mechanical vibration. Further, the force-haptic system can include a circuit board, where the sensor chip and the haptic actuator are electrically and mechanically coupled to the circuit board. The integrated circuit can be configured to process an electrical signal received from the at least one sensing element and to output the electrical excitation signal.

Abstract: Described herein is a ruggedized microelectromechanical (“MEMS”) force sensor. The sensor employs piezoresistive or piezoelectric sensing elements for force sensing where the force is converted to strain and converted to electrical signal. In one aspect, both the piezoresistive and the piezoelectric sensing elements are formed on one substrate and later bonded to another substrate on which the integrated circuitry is formed. In another aspect, the piezoelectric sensing element is formed on one substrate and later bonded to another substrate on which both the piezoresistive sensing element and the integrated circuitry are formed.

Abstract: Described herein is a ruggedized microelectromechanical (“MEMS”) force sensor. The sensor employs piezoresistive or piezoelectric sensing elements for force sensing where the force is converted to strain and converted to electrical signal. In one aspect, both the piezoresistive and the piezoelectric sensing elements are formed on one substrate and later bonded to another substrate on which the integrated circuitry is formed. In another aspect, the piezoelectric sensing element is formed on one substrate and later bonded to another substrate on which both the piezoresistive sensing element and the integrated circuitry are formed.

Abstract: Described herein is a ruggedized microelectromechanical (“MEMS”) force sensor. The sensor employs piezoresistive or piezoelectric sensing elements for force sensing where the force is converted to strain and converted to electrical signal. In one aspect, both the piezoresistive and the piezoelectric sensing elements are formed on one substrate and later bonded to another substrate on which the integrated circuitry is formed. In another aspect, the piezoelectric sensing element is formed on one substrate and later bonded to another substrate on which both the piezoresistive sensing element and the integrated circuitry are formed.

Abstract: Described herein is a ruggedized microelectromechanical (“MEMS”) force sensor. The sensor employs piezoresistive or piezoelectric sensing elements for force sensing where the force is converted to strain and converted to electrical signal. In one aspect, both the piezoresistive and the piezoelectric sensing elements are formed on one substrate and later bonded to another substrate on which the integrated circuitry is formed. In another aspect, the piezoelectric sensing element is formed on one substrate and later bonded to another substrate on which both the piezoresistive sensing element and the integrated circuitry are formed.

Abstract: Described herein is a ruggedized microelectromechanical (“MEMS”) force sensor. The sensor employs piezoresistive or piezoelectric sensing elements for force sensing where the force is converted to strain and converted to electrical signal. In one aspect, both the piezoresistive and the piezoelectric sensing elements are formed on one substrate and later bonded to another substrate on which the integrated circuitry is formed. In another aspet, the piezoelectric sensing element is formed on one substrate and later bonded to another substrate on which both the piezoresistive sensing element and the integrated circuitry are formed.

Abstract: Integrated systems for force or strain sensing and haptic feedback are described herein. An example force-haptic system can include a sensor chip configured to receive an applied force, where the sensor chip includes at least one sensing element and an integrated circuit. The force-haptic system can also include a haptic actuator configured to convert an electrical excitation signal into mechanical vibration. Further, the force-haptic system can include a circuit board, where the sensor chip and the haptic actuator are electrically and mechanically coupled to the circuit board. The integrated circuit can be configured to process an electrical signal received from the at least one sensing element and to output the electrical excitation signal.

Abstract: A semiconductor device including a VDMOS device formed therein includes a terminal, or contact, to the drain region of the VDMOS device from the frontside of the device. In one or more implementations, a semiconductor device includes a semiconductor substrate having a first surface and a second surface and a vertical diffused metal-oxide-semiconductor device formed within the semiconductor substrate. The vertical diffused metal-oxide-semiconductor device includes at least one source region formed proximate to the first surface and at least one drain region formed proximate to the second surface. A through-substrate via is formed within the semiconductor substrate, and the through-substrate via electrically connected to the drain region. The through-substrate via provides an electrical interconnection to the drain region from the first surface.

Abstract: An EEPROM memory cell with a coupler region is disclosed. The coupler region has a well and at least one feeder region formed in the well. The at least one feeder region is configured to provide majority carriers to a channel region defined in the well so that a portion of the channel region adjoining the top surface of the coupler region is inverted during an erase operation.

Abstract: Methods of forming coaxial feedthroughs for 3d integrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.

Abstract: A dynamic trim method includes testing a selected number of cells on a die with predetermined testing margins. Data from this testing is used to determine dynamic reference margins for improving yield. Advantageously, yield is improved by allowing functioning fast or slow units to pass wafer sort by applying the dynamic reference margins for varying processes.

Abstract: N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.

Abstract: Techniques are described to form a low-noise, high-gain semiconductor device. In one or more implementations, the device includes a substrate including a first dopant material having a concentration ranging from about 1×1010/cm3 to about 1×1019/cm3. The substrate also includes at least two active regions formed proximate to a surface of the substrate. The at least two active regions include a second dopant material, which is different than the first dopant material. The device further includes a gate structure formed over the surface of the substrate between the active regions. The gate structure includes a doped polycrystalline layer and an oxide layer formed over the surface between the surface and the doped polycrystalline layer. The doped polycrystalline layer includes the first dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3.

Abstract: Methods of forming coaxial feedthroughs for 3d integrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.

Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Abstract: Techniques are described to form a low-noise, high-gain semiconductor device. In one or more implementations, the device includes a substrate including a first dopant material having a concentration ranging from about 1×1010/cm3 to about 1×1019/cm3. The substrate also includes at least two active regions formed proximate to a surface of the substrate. The at least two active regions include a second dopant material, which is different than the first dopant material. The device further includes a gate structure formed over the surface of the substrate between the active regions. The gate structure includes a doped polycrystalline layer and an oxide layer formed over the surface between the surface and the doped polycrystalline layer. The doped polycrystalline layer includes the first dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3.

Abstract: A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.

Abstract: N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.

Abstract: A dynamic trim method includes testing a selected number of cells on a die with predetermined testing margins. Data from this testing is used to determine dynamic reference margins for improving yield. Advantageously, yield is improved by allowing functioning fast or slow units to pass wafer sort by applying the dynamic reference margins for varying processes.