Patents by Inventor Albert Fayrushin

Albert Fayrushin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100184282
    Abstract: A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer, removing the exposed portion of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness, forming a dielectric layer on the charge trapping layer, and forming a gate electrode on the dielectric layer.
    Type: Application
    Filed: April 1, 2010
    Publication date: July 22, 2010
    Inventor: Albert Fayrushin
  • Patent number: 7760550
    Abstract: A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Albert Fayrushin, Byung-Yong Choi
  • Publication number: 20090016110
    Abstract: A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Yong CHOI, Albert FAYRUSHIN
  • Publication number: 20090008700
    Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.
    Type: Application
    Filed: June 12, 2008
    Publication date: January 8, 2009
    Inventors: Albert Fayrushin, Byung-Yong Choi, Choong-Ho Lee