Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and a comparator that compares output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generate a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the comparator indicates that the output signal of the power semiconductor device has changed relative to the reference value.

Abstract: The disclosed inventions relate to the field of power control electronics. More specifically the disclosed inventions pertain to Power Stack Control Systems which are used to control the generation of AC power from a DC or AC input voltage. The disclosed Power Stack Control Systems include a serial interface connection, the serial interface connection being in serial electrical communication with a plurality of power stacks, the plurality of power stacks comprising at least one interface board and at least one IGBT driver board, the at least one interface board being in parallel communication with at least one IGBT driver board.

Abstract: The disclosed inventions relate to the field of power control electronics. More specifically the disclosed inventions pertain to Power Stack Control Systems which are used to control the generation of AC power from a DC or AC input voltage. The disclosed Power Stack Control Systems include a serial interface connection, the serial interface connection being in serial electrical communication with a plurality of power stacks, the plurality of power stacks comprising at least one interface board and at least one IGBT driver board, the at least one interface board being in parallel communication with at least one IGBT driver board.

Abstract: A circuit for providing gain compensation to a swept frequency response in an ultra-wideband system includes using a variable amplitude IF signal into a gigahertz mixer to control the amplitude of a ultra-wideband transmitter. The variable amplitude IF signal is generated by a multiplier receiving a fixed-level intermediate frequency (IF) signal and a gain control input. The gain control input being provided by an digital-to-analog converter controlled by gain control values in a look-up table. The values of the look-up table are generated by inverting, normalizing, and scaling the uncompensated gain response of the ultra-wideband system. The gain compensated system produces a substantially flat amplitude response at the output of a quadrature receiver.

Abstract: A power efficient hearing aid uses a programmable biasing technique to set the quiescent operating points of amplifiers used by the hearing aid to avoid excessive power usage by the hearing aid. The hearing aid also includes power supply circuitry which develops +1.25 volts and -1.25 volts relative to ground from a single +1.25 volt source. The hearing aid also conserves power by selectively disabling low frequency signal processing channels in the presence of relatively large amplitude ambient noise.

Abstract: A power efficient hearing aid uses a programmable biasing technique to set the quiescent operating points of amplifiers used by the hearing aid to avoid excessive power usage by the hearing aid. The hearing aid also includes power supply circuitry which develops +1.25 volts and -1.25 volts relative to ground from a single +1.25 volt source. The hearing aid also conserves power by selectively disabling low frequency signal processing channels in the presence of relatively large amplitude ambient noise.

Abstract: A single stage multi-rate finite impulse response filter is used as the decimating filter for a sigma-delta analog-to-digital converter. The filter uses 2048 22-bit coefficient values to produce a sampled data output signal having a sampling rate of 48 KHz and a sample resolution of 16 bits from an input signal having a sampling rate of 3.072 MHz and a sample resolution of one bit. The filter uses a single read-only memory to hold the 2048 coefficient values. The coefficient values are distributed to eight four-way multiplexed accumulators by a circuitry which includes a signal multiplexer and a barrel shifter. The accumulators use unsigned arithmetic to calculate the output sample values. A value C0, representing a normalizing offset and gain applied to each of the coefficient values, is selected such that 2048 times C0 is a value which overflows the accumulator, leaving a value of zero in the accumulator.

Abstract: A monitoring circuit incorporated into a video game display device is operated responsively to first and second non-overlapping clock pulses and monitors raster line status in comparison to a stored raster address and provides a high speed raster scan interrupt when that address is achieved, triggering a SPRITE or other feature(s) display.

Abstract: A display control circuit provides the logical determination of display information for each dot point of a color television or other display device used in connection with an electronic game for displaying up to eight "targets", as well as background information, according to a preassigned software defined priority whereby hardware circuitry encodes background-to-target software information and then decodes all game display circuit information to generate a color display code to the color television-type display device, this hardware utilizing a reduced space on a large scale integrated (LSI) circuit.

Abstract: A solid-state, digital logic, sine-cosine generator is provided for use in color television signal generators which contributes little or no phase shift or drift, whereby an input frequency of four times the color burst rate is used, and a first divide by two shift register operates upon that input signal frequency while a second divide by two shift register is used to obtain the proper color burst frequency as well as the 90.degree. relationship for the sine and cosine signals; a series of integrators then converts the digital "square" waves to triangular and then sinusoidal signals.

Abstract: An operational amplifier circuit for use in high density L.S.I. chips incorporates four solid state silicon devices in a flip-flop-like configuration including a source follower function on the input side of the circuit while a depletion transistor provides for positive feedback and prohibits the circuit from latching thereby the circuit is locked to operate in a transition zone between switching states, providing a linear high gain function which can be operated as an amplifier.