Abstract: Methods and apparatus for an ATM network for implementing a fair servicing of all connections during a back-logged condition through the use of a weighted fair queuing technique. The system is particularly suited for systems where the packets/cells are of a fixed size. Although some important approximations are made in the proposed implementation, all of the properties of an ideal weighted fair queuing algorithm are preserved. The sorting methods and apparatus are advantageous in that it is possible to maintain appropriate servicing of connections without sorting all of the individual connections. This may be accomplished by pre-sorting each of the individual virtual circuit connections into a finite number of predetermined bins according to a weight associated with the connection. Thereafter, only the bins need be sorted without having to sort each of the individual connections.

Abstract: A method and apparatus regulate the admission control of, and requests for routing of, virtual circuits in a network by determining network resource requirements for the virtual circuits. The method is generalized for the shared-memory architecture of a network node, to allocate a buffer size value, Bi, to an output port, i, for use in the effective bandwidth computation. A static allocation policy is utilized to allocate the available buffer, BSMF, to each output port, i. The allocated buffer is determined by selecting a value from a range having a lower bound obtained by partitioning the buffer, BSMF, to evenly divide the buffer space among all the output ports, such that ? i ? B i = B SMF ; and having an upper bound obtained by using the total available buffer, BSMF, for each port in their computation of effective bandwidths. The network resource requirements are based on a set of parameters used to control the flow of information from a communications device onto the virtual circuit.

Abstract: Methods and apparatus for an ATM network for implementing a fair servicing of all connections during a back-logged condition through the use of a weighted fair queuing technique. The system is particularly suited for systems where the packets/cells are of a fixed size. Although some important approximations are made in the proposed implementation, all of the properties of an ideal weighted fair queuing algorithm are preserved. The sorting methods and apparatus are advantageous in that it is possible to maintain appropriate servicing of connections without sorting all of the individual connections. This may be accomplished by pre-sorting each of the individual virtual circuit connections into a finite number of predetermined bins according to a weight associated with the connection. Thereafter, only the bins need be sorted without having to sort each of the individual connections.

Abstract: A method and apparatus regulate the admission control of, and requests for routing of, virtual circuits in a network by determining network resource requirements for the virtual circuits. The method is generalized for the shared-memory architecture of a network node, to allocate a buffer size value, Bi, to an output port, i, for use in the effective bandwidth computation. A static allocation policy is utilized to allocate the available buffer, BSMF, to each output port, i. The allocated buffer is determined by selecting a value from a range having a lower bound obtained by partitioning the buffer, BSMF, to evenly divide the buffer space among all the output ports, such that &Sgr;iBi=BSMF; and having an upper bound obtained by using the total available buffer, BSMF, for each port in their computation of effective bandwidths. The network resource requirements are based on a set of parameters used to control the flow of information from a communications device onto the virtual circuit.

Abstract: Methods and apparatus for an ATM network for determining an allowed cell rate without the introduction of oscillations by using a average cell rate of all virtual circuits. Each ATM switch may be configured to calculate an allowed cell rate (ACR) for each connection between adjacent ATM switches along the virtual circuit and to relay this information back to a source using a BRM cell.

Abstract: A high capacity packet switch is implemented using an expansion module that divides an incoming packet cell into a plurality of segments and supplies the segments, based on their sequential order, to respective ones of a plurality of concentrator units contained in the expansion module. Each concentrator unit includes a plurality of concentrator logic units and one of those logic units accepts a segment for storage based on routing information contained in the packet cell. The stored segments forming a packet cell are thereafter unloaded and recombined in proper sequence for routing to a packet switch module, which then forwards the packet cell toward its destination.