Patents by Inventor Albert Loh

Albert Loh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10361146
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 23, 2019
    Assignee: UTAC Headquarters PTE, LTD.
    Inventors: Saravuth Sirinorakul, Keith M. Edwards, Suebphong Yenrudee, Albert Loh
  • Publication number: 20190181077
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.
    Type: Application
    Filed: January 9, 2019
    Publication date: June 13, 2019
    Applicant: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Keith M. Edwards, Suebphong Yenrudee, Albert Loh
  • Patent number: 10276477
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 30, 2019
    Assignee: UTAC Headquarters PTE. LTD.
    Inventors: Saravuth Sirinorakul, Keith M. Edwards, Suebphong Yenrudee, Albert Loh
  • Patent number: 9196504
    Abstract: Embodiments of the present invention are directed to a thermal leadless array package with die attach pad locking feature and methods of producing the same. A copper layer is half-etched on both surfaces to define an array of package contacts and a die attach pad. Each die attach pad is fully embedded in encapsulate material to provide a positive mechanical locking feature for better reliability. In some embodiments, the contacts include four active corner contacts.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 24, 2015
    Assignee: UTAC DONGGUAN LTD.
    Inventors: Albert Loh, Edward Then, Serafin Pedron, Jr., Saravuth Sirinorakul
  • Publication number: 20140008777
    Abstract: Embodiments of the present invention are directed to a thermal leadless array package with die attach pad locking feature and methods of producing the same. A copper layer is half-etched on both surfaces to define an array of package contacts and a die attach pad. Each die attach pad is fully embedded in encapsulate material to provide a positive mechanical locking feature for better reliability. In some embodiments, the contacts include four active corner contacts.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Applicant: UTAC DONGGUAN LTD
    Inventors: Albert LOH, Edward THEN, Serafin PEDRON, JR., Saravuth Sirinorakul
  • Patent number: 6597188
    Abstract: A new ground land is provided on the BGA package that allows for increasing the test sensitivity of a wire bond tester. The ground land is interconnected with a ground ring that is provided in the immediate vicinity of the BGA device. The ground land of the invention is provided such that the location of the ground land does not unduly interfere with essential functions and locations of other components that are required for the mounting of the BGA device, most preferably in a corner of the BGA device package.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: July 22, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Dexter Reynoso, Beng Kee Lim, Tuck Chee Albert Loh
  • Patent number: 6319418
    Abstract: A new pattern is provided for the bus lines that are used to facilitate plating of layers of electrical lines that form a Printed Circuit Board. Where Prior Art bus lines have a straight-line geometry, the bus lines of the invention have any geometry that is not a straight-line geometry. The geometry of the bus lines of the invention can be of any design as long as this design allows for interrupted cutting of the bus line, that is the cutting tool does not, during the process of cutting the bus line, make constant and continuous contact with the bus line.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: November 20, 2001
    Assignee: St. Assembly Test Services Pte Ltd.
    Inventors: Arvin Verdeflor, Albert Loh, Steven Liew, William S. Villaviray