Abstract: A low cost method of producing proper source/drain junctions and transistor characteristics is disclosed. Through consolidation of masking steps, source/drain processing has a significantly lower cost with no performance loss. A blanket boron implant is employed as both a PLDD implant for the PMOS and a halo region implant for the NMOS. After formation of sidewall spacers on the gates, a masked arsenic and phosphorous implant is employed as a N+ implant. Because the phosphorous drives in faster than the arsenic, the desired N+/NLDD/halo architecture is generated. A masked boron implant is then employed as the P+ implant. Thus, the source/drain junctions are formed using only two masked implants. In an alternative embodiment, a third masked implant of phosphorous is used to form the NLDD junction prior to the sidewall spacer deposition instead of phosphorous being implanted with the arsenic.

Abstract: The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing a metal line that shorts all of the gate contacts together, and overlies each of the gates. By reducing the gate resistance, the maximum frequency f.sub.MAX of the multi-finger transistor can be increased.

Abstract: In a high-voltage MOS transistor that utilizes a lightly-doped drain region to isolate a heavily-doped drain region from the substrate, the reverse bias which can be applied across the drain-to-substrate junction of the transistor is increased by reducing the width of the heavily-doped drain region.

Abstract: In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

Abstract: In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

Abstract: A series of self-aligned, intermediate strips of conductive material, which contact each of the drain regions in a corresponding number of columns of drain regions in a flash electrically programmable read-only-memory (EPROM), are formed as a thick layer of planarized polysilicon. By utilizing intermediate strips of conductive material which are formed from a thick layer of polysilicon, the formation of cracks or voids in the intermediate strips of conductive material can be eliminated.

Abstract: The bit lines in an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), are formed by utilizing a plurality of field oxide regions and a plurality of pairs of dielectric/floating gate strips, which have the ends of each pair of strips connected together over a field oxide region, as an implant mask. By connecting together the ends of each pair of dielectric/floating gate strips, the width of the strips at the edges of the field oxide regions will remain constant. As a result, the isolation between adjacent bit lines, which is defined by the width of the strips, will also remain constant.

Abstract: The current driven by the segment select transistors of an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), is increased by eliminating the even numbered segment select transistors in every other row of segment select transistors, and the odd numbered segment select transistors in the remaining rows, and by changing the current path through the segment so that the current flows from a segment select transistor in one row of segment select transistors to a segment select transistor in an adjacent row of transistors. By eliminating every other segment select transistor in each row of transistors, the maximum pitch of the segment select transistors can be substantially increased, thereby providing the required programming current, while at the same time maintaining the required isolation between adjacent segment select transistors.

Abstract: Each byte of data in a high-density, electrically-erasable, programmable read-only-memory (EEPROM) cell array is selectively erased by forming a plurality of memory cells in each of a plurality of P-wells where the memory cells in each P-well are formed one byte wide by n rows in length. By forming the memory cells in each P-well to be one byte wide by n rows in length, each byte of data can be selectively erased by identifying the corresponding P-well and the row within the P-well.

Abstract: The memory array of a high density, electrically-erasable, programmable read-only-memory (EEPROM) is divided into a series of segments which are individually accessible via a plurality of segment select transistors. When a specific memory cell or cells is to be read, only the segment select transistors which correspond to the segment of memory which contains the specific memory cell or cells are turned on. As a result, the time required to access the specific memory cell or cells can be significantly reduced.

Abstract: The current driven by the segment select transistors of an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), is increased by eliminating the even numbered segment select transistors in every other row of segment select transistors, and the odd numbered segment select transistors in the remaining rows, and by changing the current path through the segment so that the current flows from a segment select transistor in one row of segment select transistors to a segment select transistor in an adjacent row of transistors. By eliminating every other segment select transistor in each row of transistors, the maximum pitch of the segment select transistors can be substantially increased, thereby providing the required programming current, while at the same time maintaining the required isolation between adjacent segment select transistors.

Abstract: The floating gate of a virtual-ground flash electrically programmable read-only-memory (EPROM) cell, which is formed over a portion of a pair of vertically-adjacent field oxide regions, is self aligned to the field oxide regions by utilizing a stacked etch process to define the widths of both the floating gate and the field oxide regions. As a result, the pitch of the cells in the X direction can be substantially reduced.

Abstract: The memory array of a high density, electrically-erasable, programmable read-only-memory (EEPROM) is divided into a series of segments which are individually accessible via a plurality of segment select transistors. When a specific memory cell or cells is to be read, only the segment select transistors which correspond to the segment of memory which contains the specific memory cell or cells are turned on. As a result, the time required to access the specific memory cell or cells can be significantly reduced.

Abstract: A method of forming a contactless EPROM cell inlcudes an initial step of forming an N+ source line in a silicon substrate. First and second N+ drain lines are then formed in parallel with and spaced-apart from the source line on opposite sides of the source line. First and second field oxide strips are formed in parallel with, but spaced-apart from the first and second drain lines, respectively, such that the source line/drain line structure is bounded on both sides by the first and second field oxide strips to separate the structure from adjacent source/drain line structures. First and second poly 1 lines overly the channel regions between the first drain line and the source line and the second drain line and the source line respectively, and are separated therefrom by a first layer of dielectric material. A plurality of spaced-apart, parallel poly 2 word lines overly and run perpendicular to the first and second poly 1 lines and are spaced-apart therefrom by a second dielectric material.

Abstract: A process flow for fabricating a self-aligned stacked gate EPROM cell that uses a CVD tantalum oxide film to replace ONO as a control gate dielectric. Tungsten replaces polysilicon as the control gate. Both the dielectric deposition and cell definition steps of the process flow are performed in a back-end module to improve dielectric integrity in the memory cells by minimizing high temperature exposure of the tantalum oxide film.

Abstract: Two process flows are disclosed for the stacked etch fabrication of an EPROM array that utilizes cross-point cells with internal access transistors. In each process flow, the edges of the poly 1 floating gates parallel to the poly 2 word line are self-aligned to the word line, eliminating parasitic poly 2 transistors and process requirements for coping with such transistors.

Abstract: The present invention provides a 5V only, EPROM memory cell structure that is utilizable in high speed UV-erasable or flash EPROM contactless arrays and that uses source side injection for programming. The EPROM cell structure comprises spaced-apart N-type source and drain regions that define a channel region in a P-type substrate. A first layer of insulating material overlies the channel region. A polysilicon (poly 1) floating gate is formed on the first insulating layer and overlies a first portion of the channel region that extends from the drain region to a point in the channel region intermediate the source and drain regions thereby defining a second portion of the channel region that extends from the intermediate point to the source region and over which the floating gate does not extend. The poly 1 floating gate also includes a coupling portion that extends over the field oxide that defines the active device area in which the EPROM cell is formed.

Abstract: A method for fabricating a split-gate EPROM cell utilizing stacked etch techniques is provided. In accordance with a preferred embodiment of the method, a layer of silicon dioxide is formed on a P- silicon substrate. A layer of polysilicon is formed on the silicon dioxide layer, followed by growth of an oxide/nitride/oxide (ONO) layer. The ONO and polysilicon layers are etched to define floating gates. Next, an edge of each floating gate is utilized in a self-aligned implant of buried N+ bit lines. The floating gate extends only over a first portion of the channel defined between the adjacent buried bit lines. A differential oxide layer is grown on the substrate between adjacent floating gates in a low temperature steam oxidation step. That is, the oxide formed over the exposed portion of the buried N+ bit line is thicker than the oxide formed over the exposed portion of the channel.

Abstract: A semiconductor electrically programmable read only memory (EPROM) contains an array of memory cells that store data which is erased when the EPROM is exposed to radiation, and also contains redundant memory circuitry. The redundant memory circuit includes one or more rows or columns of redundant memory cells. A programmable redundancy control circuit determines, for each row or column of redundant memory cells, which row or column of defective memory cells it will be used to replace. The programmable redundancy control circuit has a plurality of non-erasable EPROM cells. Distinct metal connection lines, formed from a first metal layer, are coupled to the drain region of each non-erasable EPROM cell for detecting the data stored therein. A metal shield, formed from a second metal layer, overlies the non-erasable EPROM cells and the metal connection lines. Further, vertical metal walls coupled to the metal shield at least partially block radiation from entry under the metal shield.