Patents by Inventor Albert Molina

Albert Molina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8831133
    Abstract: Recursive digital pre-distortion (DPD) techniques are provided. Digital pre-distortion is performed by applying a signal to a recursive system to generate a state vector; providing the state vector as a feedback value to the recursive non-linear system; and applying the state vector to a second function to generate an output signal, wherein at least one of the recursive system and the second function comprise a non-linear function. The recursive non-linear system can be initialized to a known initial value. The recursive system is defined by a system of non-linear differential equations.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: September 9, 2014
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Albert Molina
  • Patent number: 8811927
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 19, 2014
    Assignee: Agere Systems LLC
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Publication number: 20140108477
    Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.
    Type: Application
    Filed: October 26, 2012
    Publication date: April 17, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Meng-Lin Yu, Joseph H. Othmer, Joseph Williams, Albert Molina
  • Publication number: 20140086361
    Abstract: A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software instructions for at least one non-linear function having at least one user-specified parameter, performing the following steps: invoking at least one functional unit that implements the at least one software instruction to apply the non-linear function to the input value, x; and generating an output corresponding to the non-linear function for the input value, x. The user-specified parameter can optionally be loaded from memory into at least one register.
    Type: Application
    Filed: October 26, 2012
    Publication date: March 27, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Meng-Lin Yu, Steven C. Pinault, Joseph Williams, Albert Molina
  • Publication number: 20140086356
    Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
    Type: Application
    Filed: October 26, 2012
    Publication date: March 27, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Chengzhou Li, Albert Molina, Joseph H. Othmer, Steven C. Pinault, Meng-Lin Yu, Joseph Willimas, Ramon Sanchez Perez, Jian-Guo Chen
  • Publication number: 20140072073
    Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.
    Type: Application
    Filed: October 26, 2012
    Publication date: March 13, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Meng-Lin Yu, Ramon Sanchez Perez
  • Publication number: 20140075162
    Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.
    Type: Application
    Filed: October 26, 2012
    Publication date: March 13, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Parakalan Venkataraghavan, Meng-Lin Yu, Joseph Williams
  • Publication number: 20130336144
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Application
    Filed: August 16, 2013
    Publication date: December 19, 2013
    Applicant: Agere Systems LLC
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Patent number: 8595604
    Abstract: A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 26, 2013
    Assignee: LSI Corporation
    Inventors: Samer Hijazi, Carl Murray, Joseph H. Othmer, Albert Molina, Kameran Azadet
  • Patent number: 8553814
    Abstract: In a communication receiver, timing recovery circuitry includes a loop filter associated with a timing recovery loop of a first communication device. The first communication device is in communication with a second communication device prior to a temporary power down/power up sequence in the first communication device. The loop filter is configured to: (i) temporarily disable at least a portion of the timing recovery loop after the temporary power down/power up sequence in the first communication device; and (ii) initiate a progression through a set of potential sampling phases to determine a given sampling phase at which the first communication device can recommence communication with the second communication device.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: October 8, 2013
    Assignee: LSI Corporation
    Inventors: Albert Molina, Oisin Ó Cuanacháin, Ramon Sanchez
  • Patent number: 8515376
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 20, 2013
    Assignee: Agere Systems LLC
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Publication number: 20130080855
    Abstract: A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Samer Hijazi, Carl Murray, Joseph H. Othmer, Albert Molina, Kameran Azadet
  • Patent number: 8385489
    Abstract: Methods and apparatus are provided for wireless channel estimation using interpolation elimination in the Eigen domain. Channel components at known OFDM symbol locations are interpolated to other OFDM symbol locations. Methods and apparatus are provided for interpolating in the Eigen domain between reference signals (i.e., training signals) to estimate the equalizer coefficients with a reduced complexity. In particular, one aspect of the present invention performs the required interpolation before a required matrix inversion in the Eigen domain.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: February 26, 2013
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Samer Hijazi, Albert Molina, Joe H. Othmer, Ramon Sanchez
  • Publication number: 20130028342
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 31, 2013
    Applicant: AGERE SYSTEMS LLC
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Patent number: 8290462
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: October 16, 2012
    Assignee: Agere Systems LLC
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Patent number: 8015226
    Abstract: Methods and apparatus are provided for performing reduced complexity discrete Fourier transforms using interpolation An input sequence of length N is transformed by extending the input sequence to an extended input sequence of length M, where M is greater than N (a power of two greater than N); performing a discrete Fourier Transform (DFT), such as a power-of-two DFT, on the extended input sequence to obtain an interpolated sequence; and applying a conversion matrix to the interpolated sequence to obtain a DFT output for the input sequence of length N. The input sequence of length N can be extended to an extended input sequence of length M, for example, by employing a zero padding technique, a cyclic extension technique, a windowing of a cyclic extended sequence technique or a resampling-based interpolation technique to extend the input sequence. The conversion matrix is substantially a sparse matrix.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: September 6, 2011
    Assignee: Agere Systems Inc.
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Publication number: 20110051867
    Abstract: Methods and apparatus are provided for wireless channel estimation using interpolation elimination in the Eigen domain. Channel components at known OFDM symbol locations are interpolated to other OFDM symbol locations. Methods and apparatus are provided for interpolating in the Eigen domain between reference signals (i.e., training signals) to estimate the equalizer coefficients with a reduced complexity. In particular, one aspect of the present invention performs the required interpolation before a required matrix inversion in the Eigen domain.
    Type: Application
    Filed: August 25, 2009
    Publication date: March 3, 2011
    Inventors: Kameran Azadet, Samer Hijazi, Albert Molina, Joe H. Othmer, Ramon Sanchez
  • Publication number: 20110026650
    Abstract: In a communication receiver, timing recovery circuitry includes a loop filter associated with a timing recovery loop of a first communication device. The first communication device is in communication with a second communication device prior to a temporary power down/power up sequence in the first communication device. The loop filter is configured to: (i) temporarily disable at least a portion of the timing recovery loop after the temporary power down/power up sequence in the first communication device; and (ii) initiate a progression through a set of potential sampling phases to determine a given sampling phase at which the first communication device can recommence communication with the second communication device.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 3, 2011
    Inventors: Albert Molina, Oisin Ó Cuanacháin, Ramon Sanchez
  • Publication number: 20100304687
    Abstract: Methods and apparatus are provided for simultaneous estimation of frequency offset and channel response for a communication system, such as a MU-MIMO communication system. An iterative method is provided for estimating frequency offset and channel response for a plurality of frequency resources. The channel response is estimated for a set of users sharing a given one of the frequency resources. In addition, the frequency offset is estimated for the users in the set, wherein the channel response and frequency offset of users not in the set are maintained at their latest updated values. Initially, the channel response of a user can be an ideal channel response and the frequency offset can be approximately zero.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Inventors: Kameran Azadet, Samer Hijazi, Albert Molina, Ramon Sanchez
  • Publication number: 20100197264
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 5, 2010
    Applicant: Agere Systems Inc.
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez