Abstract: A method and apparatus for low pin count firmware hub recovery on a circuit board having a firmware hub includes coupling a firmware hub recovery module having a firmware program onto the circuit board, establishing communication between a central processing unit (CPU) and the firmware hub recovery module, and reprogramming the firmware hub by the firmware program.

Abstract: A method and apparatus for programming firmware on a circuit board without powering the entire circuit board includes a firmware interface which can be isolated from the rest of the circuit board and a logic module for programming the firmware. The firmware interface includes a connector which supports powering the circuit board as well as permitting programming from the logic module.

Abstract: An improved power management system provides a dual mode power supply that supplies normal voltages and standby voltages. When the computer is placed in a power saving mode, the power supply is controlled to cease supplying the normal voltages to conserve power. While the computer is in the power saving mode, the standby power is supplied to specific devices that may be involved in waking the computer. When an I/O device or another device detects computer activity while in the power saving mode, a wake signal is generated and input to a power management device. The power management device then controls the power supply to supply the normal voltages to wake the computer.

Abstract: A computer includes a dual mode power supply that includes a main voltage converter and a standby voltage converter. The main voltage converter generates a main operating voltage at a normal operating current. The standby voltage generator generates a standby voltage at a standby current. The power supply outputs a dual mode output that includes both the main voltage and the standby voltage. The standby current is less than the normal operating current. The computer includes a host processor, a memory array, and a wake-up device. A power management device is coupled to the host processor and receives at least the standby voltage. The dual mode output from the power supply is input to the wake-up device and the memory array to allow the computer to be placed in a power saving mode by terminating supply of the main voltage. While in the power saving mode and receiving only the standby voltage, the wake-up device can wake-up the computer.

Abstract: A flexible non-volatile memory controller that provides external boot block protection and provides support for non-volatile memory devices having different sizes is disclosed. The flexible non-volatile memory controller includes a boot block protection unit that provides external boot block protection for a non-volatile memory device without internal boot block protection. The boot block protection unit prevents external devices from writing to a prespecified block of memory in the non-volatile memory device in a normal mode. The flexible non-volatile memory controller also includes a memory expansion unit that is adapted to control non-volatile memory devices having different sizes.

Abstract: The reset circuit including a logic gate coupled to an electrical component containing the CMOS memory. The logic gate includes an output and at least a first and second inputs. The first input is configured to receive a first signal indicating that a power-down sequence has been requested. The second input, however, is configured to receive a second signal being a system reset signal. As a result, during a power-down sequence, CMOS memory is precluded from being accessed almost immediately after the first signal has been deactivated while other devices are powered-down in a normal fashion.