Abstract: An Internet of Things (IoT) technique for vehicular traffic management, including an IoT sensor to measure traffic data of vehicular traffic, a traffic analyzer to determine a traffic event based on the traffic data, and an IoT gateway to issue a response based on the traffic event.

Abstract: A liquid composition includes copper particles, an organic acid, and a solvent. The copper particle has a particle size of 0.5 ?m˜30 ?m which falls in a micron scale. The liquid composition performs reaction sintering by redox reactions taken place between the copper particles and an organic acid solution at a low temperature of 150° C. in order to produce a dense copper layer and improve the conventional micron-scale copper particles that requires a protective atmosphere for the high-temperature sintering before achieving the required densification. This liquid composition also prevents an excessive oxidation of the nano copper particles during the low-temperature sintering process and a failure of the dense sintering. Due to the agglomeration of nano copper particles, some areas have to be sintered first, so that the sintered products have a good uniformity of tissue and a low resistance below 0.04 ohm per square (?/?).

Abstract: A liquid composition includes copper particles, an organic acid, and a solvent. The copper particle has a particle size of 0.5 ?m˜30 ?m which falls in a micron scale. The liquid composition performs reaction sintering by redox reactions taken place between the copper particles and an organic acid solution at a low temperature of 150° C. in order to produce a dense copper layer and improve the conventional micron-scale copper particles that requires a protective atmosphere for the high-temperature sintering before achieving the required densification. This liquid composition also prevents an excessive oxidation of the nano copper particles during the low-temperature sintering process and a failure of the dense sintering. Due to the agglomeration of nano copper particles, some areas have to be sintered first, so that the sintered products have a good uniformity of tissue and a low resistance below 0.04 ohm per square (?/?).

Abstract: A cargo container security system and method, including a cargo container with at least one sensor for detecting an open or closed status of a door on the cargo container and a geographic positioning locator for identifying a location of the cargo container. A control unit, located on the cargo container and operatively connected to the at least one sensor and geographic positioning locator, continuously receives historical data corresponding to at least the status of the cargo container door and location of the cargo container while the cargo container is in transit. The control unit assigns a timestamp to the received historical data, and stores the received historical data and associated timestamp in memory. A central computer system receives and analyzes the stored historical data for any anomalies upon the arrival of the cargo container at a destination. The central computer system generates an alert if an anomaly is identified.

Abstract: A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows and other higher temperature processes.

Abstract: A thermally controlled, anti-shock apparatus for protecting an automotive electronic device. The apparatus includes a first housing having sidewalls that define an interior cavity. A second housing having a reservoir containing fluid is disposed within the interior cavity of the first housing. A sealed housing for carrying the electronic device is disposed within the fluid in the reservoir of the second housing, wherein the fluid provides buoyancy for keeping the sealed housing at least partially afloat within the reservoir. The sealed housing includes an inner fluid impermeable bag for enclosing the protected electronic device and an outer fluid impermeable bag in which the inner bag and electronic device are disposed. A cooling system condenser includes condenser tubing connected to one or more heat dissipating members that are mounted on a thermally conductive panel using one or more high strength magnets.

Abstract: A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows and other higher temperature processes.

Abstract: A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

Abstract: A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

Abstract: A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated region formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

Abstract: A method is disclosed for creating a sub-minimum opening in a semiconductor device, comprising the steps of: a) providing a first layer; b) providing a second layer over said first layer; c) providing a third layer over said second layer; d) providing a photoresist mask over said third layer; e) etching said third layer to form defined structures; f) depositing a fourth layer for forming spacers; g) etching said fourth layer to form said spacers; and h) etching said first layer to form an opening in said first layer. In etching the fourth layer to form the spacers, the third layer is generally etched away to form an opening to the first layer, and, in the following step, an opening (or feature) can be etched on the first layer. Generally speaking, the first and third layers can be of any material and should have similar etching rate; the second and fourth layers can be of any material and should have similar etching rate.

Abstract: A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

Abstract: A sun-synchronous sun ray blocking device for use in a spacecraft having a directionally controlled main body, such as a low inclination angle earth (as well as other planets) orbit spacecraft, that is, a three axis stabilized spacecraft having north, south, east, west, earth and anti-earth panels defining a spacecraft main body. The north and south panels, on which the spacecraft equipment with high heat dissipation is usually mounted, have their planar normal axes relatively parallel to the spinning axis of the earth. Normal to each of the north and south panel, a solar panel loaded with solar cells is extended and is directly rotating about the same axis. The solar panels are controlled in such a way that the solar cells side of the panels always faces the sun.

Abstract: An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.

Abstract: A process for forming GaAs on a silicon substrate with very low levels of unintended silicon doping. First, a dielectric layer of silicon dioxide, silicon nitride, or both is grown or deposited on the substrate. Next, a window is opened in the dielectric layer exposing the silicon substrate in the regions in which the GaAs is to be formed. The GaAs layer is then formed on the substrate using conventional techniques with the gas phase transfer of silicon contamination from the edges and back of the silicon substrate to the GaAs region inhibited by the dielectric layer or layers.

Abstract: An electrically programmable and eraseable memory element using source-side hot-electron injection. A semi-conductor substrate of a first conductivity type is provided with a source region and a drain region of opposite conductivity type and a channel region of the first conductivity type extending between the source and drain regions. A control gate overlies the channel region, and a floating gate insulated from the control gate, the source and drain regions and the channel region is located either directly underneath the control gate over the channel region, partially underneath the control gate over the channel region or spaced to the source side of the control gate. A weak gate control region is provided in the device near the source so that a relatively high channel electric field for promoting hot-electron injection is created under the weak gate control region when the device is biased for programming.