Abstract: A low-noise high-speed output buffer receives digital control signals for varying the switching delay and di/dt of the buffer. For a plurality of output buffers, one buffer is used to determine the digital control signal values for the rest. The switching delay is controlled by referencing the one output buffer's delay to a clock cycle (e.g., 0.75 T or T, where T equals the clock cycle period). The digital control signal values which define the delay with reference to the clock cycle also determine the di/dt for the output buffers. As process or operating conditions vary, the control signal values change to maintain the delay in the prescribed relation to the clock cycle. Accordingly, the absolute di/dt values change. Thus, the output signal is available by the time needed (e.g., 0.75 T), while the di/dt is varied to an optimum setting based on the absolute delay time.