Patents by Inventor Alberto Perelli

Alberto Perelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for forming a morphological edge structure to seal integrated electronic devices
    Patent number: 6022762
    Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: February 8, 2000
    Assignee: STMicroelectronics S.R.L.
    Inventor: Alberto Perelli
  • Process for forming a morphological edge structure to seal integrated electronic devices, and corresponding device
    Patent number: 5969408
    Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: October 19, 1999
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Alberto Perelli