Abstract: Embodiments of the present invention are directed to a computer-implemented method for process management. The method includes assigning a drawer and a physical processor to each element of a first ready queue pointer array, wherein each element of the first ready queue pointer array is configured to point to a memory address of a ready queue header. The method further includes assigning the drawer and the physical processor to each element of a second ready queue pointer array, wherein each element of the second ready queue pointer array is configured to point to the same ready queue header as a respective element of the first ready queue pointer array. The method further includes detecting that either a physical processor has become unavailable to process executable instructions or that a ready queue is empty. The method further includes allocating an available physical processor and a ready queue with executable instructions.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for process management. The method includes assigning a drawer and a physical processor to each element of a first ready queue pointer array, wherein each element of the first ready queue pointer array is configured to point to a memory address of a ready queue header. The method further includes assigning the drawer and the physical processor to each element of a second ready queue pointer array, wherein each element of the second ready queue pointer array is configured to point to the same ready queue header as a respective element of the first ready queue pointer array. The method further includes detecting that either a physical processor has become unavailable to process executable instructions or that a ready queue is empty. The method further includes allocating an available physical processor and a ready queue with executable instructions.

Abstract: According to one embodiment, a system includes a data storage device having data stored therein and a native computer system having resident thereon a controlling operating system in communication with the data storage device. The system also includes a primary computer system having resident thereon a primary operating system in communication with the native computer system via a first connection, the primary computer system being in communication with the data storage device via a second connection that is not in communication with the native computer system, the primary computer system having a processor executing a primary application. A volume on the data storage device is under logical control of the controlling operating system of the native computer system, and the primary computer system reads or writes data to the volume directly via the second connection. Other systems, methods and computer program products are also described relating to accessing data.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: In one embodiment, a system includes at least one outgoing transmission engine implemented in hardware, wherein the at least one outgoing transmission engine is for transmitting data in the plurality of buffers queued to the at least one outgoing transmission engine to the intersystem transmission medium, and a memory for storing the plurality of buffers, wherein each of the buffers queued to the at least one outgoing transmission engine is dequeued after the data is transmitted therefrom and requeued to an available buffer queue. In another embodiment, a system includes the above, except that it includes one or more incoming reception engines instead of outgoing transmission engines. In another embodiment, a method includes buffering data to be sent out by executing a loop of commands on an intersystem communication device and disconnecting the buffers after data has been transferred.

Abstract: Work units are transparently offloaded from a main processor to offload processing systems for execution. For a particular work unit, a suitable offload processing system is selected to execute the work unit. This includes determining the requirements of the work unit, including, for instance, the hardware and software requirements; matching those requirements against a set of offload processing systems with an arbitrary set of available resources; and determining if a suitable offload processing system is available. If a suitable offload processing system is available, the work unit is scheduled to execute on that offload processing system with no changes to the work unit itself. Otherwise, the work unit may execute on the main processor or wait to be executed on an offload processing system.

Abstract: Work units are transparently offloaded from a main processor to offload processing systems for execution. For a particular work unit, a suitable offload processing system is selected to execute the work unit. This includes determining the requirements of the work unit, including, for instance, the hardware and software requirements; matching those requirements against a set of offload processing systems with an arbitrary set of available resources; and determining if a suitable offload processing system is available. If a suitable offload processing system is available, the work unit is scheduled to execute on that offload processing system with no changes to the work unit itself. Otherwise, the work unit may execute on the main processor or wait to be executed on an offload processing system.

Abstract: Work units are transparently offloaded from a main processor to offload processing systems for execution. For a particular work unit, a suitable offload processing system is selected to execute the work unit. This includes determining the requirements of the work unit, including, for instance, the hardware and software requirements; matching those requirements against a set of offload processing systems with an arbitrary set of available resources; and determining if a suitable offload processing system is available. If a suitable offload processing system is available, the work unit is scheduled to execute on that offload processing system with no changes to the work unit itself. Otherwise, the work unit may execute on the main processor or wait to be executed on an offload processing system.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: According to one embodiment, a system includes a data storage device having data stored therein and a native computer system having resident thereon a controlling operating system in communication with the data storage device. The system also includes a primary computer system having resident thereon a primary operating system in communication with the native computer system via a first connection, the primary computer system being in communication with the data storage device via a second connection that is not in communication with the native computer system, the primary computer system having a processor executing a primary application. A volume on the data storage device is under logical control of the controlling operating system of the native computer system, and the primary computer system reads or writes data to the volume directly via the second connection. Other systems, methods and computer program products are also described relating to accessing data.

Abstract: In one embodiment, a system includes at least one outgoing transmission engine implemented in hardware, wherein the at least one outgoing transmission engine is for transmitting data in the plurality of buffers queued to the at least one outgoing transmission engine to the intersystem transmission medium, and a memory for storing the plurality of buffers, wherein each of the buffers queued to the at least one outgoing transmission engine is dequeued after the data is transmitted therefrom and requeued to an available buffer queue. In another embodiment, a system includes the above, except that it includes one or more incoming reception engines instead of outgoing transmission engines. In another embodiment, a method includes buffering data to be sent out by executing a loop of commands on an intersystem communication device and disconnecting the buffers after data has been transferred.