Patents by Inventor Alberto Sandbank

Alberto Sandbank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active
    Patent number: 5822779
    Abstract: A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ("BIU") which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: October 13, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Gideon Intrater, Ohad Falik, Aharon Ostrer, Yair Baydatch, Alberto Sandbank
  • Testing hooks for testing an integrated data processing system
    Patent number: 5638306
    Abstract: The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core. The system also includes test hook functions for facilitating production testing of the system.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: June 10, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Gideon Intrater, Oved Oz, Alberto Sandbank
  • Integrated data processing system including CPU core and parallel, independently operating DSP module
    Patent number: 5592677
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: January 7, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
  • Integrated CPU core and parallel, independently operating DSP module and time-critical core priority scheme
    Patent number: 5590357
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: December 31, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank