Abstract: One or more boost circuits are included within each row of CAM cells to increase the charging rate of its match line during match conditions. The CAM cells in each row control corresponding match transistors connected in series between a supply voltage and a match line. The match transistors collectively form a NAND match circuit. A boost circuit connected between a supply voltage and ground potential is coupled to a midpoint of the NAND match transistor chain. During compare operations, if all CAM cells match, all match transistors turn on and pull the match line toward the supply voltage. As the voltage at the midpoint of the match line reaches a threshold voltage, the boost circuit provides an additional charging path to more quickly charge the match line. If any CAM cell mismatches, its match transistor turns off and isolates the match line from the supply voltage.

Abstract: An improved gate oxide protected level shifter is provided which has a higher speed of operation than is traditionally available. The level shifter includes a first capacitor coupled between a first output terminal and the input of an inverter and a second capacitor coupled between a first node and the output of the inverter. As a result, the speed of the transitions at the gates of the pair of cross-coupled P-channel MOS transistors is increased several times.

Abstract: A reference voltage generation circuit is provided for use in gate oxide protected circuits for generating an NMOS reference voltage and PMOS reference voltage in which the NMOS reference voltage is independent of an I/O buffer power supply potential and in which the PMOS reference voltage tracks the supply voltage. The reference voltage generation circuit includes a bandgap voltage reference circuit, a first operational amplifier, a voltage divider and a second operational amplifier. In one embodiment, the NMOS reference voltage is approximately +2.2 volts and is referenced with respect to ground. The PMOS reference voltage is approximately +1.1 volts and referenced with respect to the I/O buffer power supply voltage and the NMOS reference voltage.

Abstract: A measurement circuit in the output circuit of a sensor detects the polarity of a source to which a load is connected. The detection of one of the two polarities establishes one of two states which is stored in a storing element and the correct one of two drivers is switched to the output terminals. This state is maintained for as long as there is no change to the polarity at the output terminals. If the terminals are interchanged, then the measurement circuit correctly restores the stored state, so that the correct driver is associated with the load in each case. If positive instead of negative switching sensors are required, there is no need to replace the equipment. When the voltage is turned on, the equipment is initialized, so that it is set in accordance with the new circumstances.