Patents by Inventor Alejandro Flavio Gonzalez

Alejandro Flavio Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for implementation of PLL minimum frequency via voltage comparison
    Patent number: 8513992
    Abstract: A method and apparatus for implementation of PLL minimum frequency via voltage comparison have been described.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: August 20, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Amit Majumder, Praveen Rajan Singh, Alejandro Flavio Gonzalez
  • DRAM interface circuits that support fast deskew calibration and methods of operating same
    Patent number: 7555668
    Abstract: A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: June 30, 2009
    Assignee: Integrated Device Technology, Inc.
    Inventors: Paul Joseph Murtagh, Prashant Shamarao, Alejandro Flavio Gonzalez
  • DRAM interface circuits that support fast deskew calibration and methods of operating same
    Publication number: 20080022145
    Abstract: A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 24, 2008
    Inventors: Paul Joseph Murtagh, Prashant Shamarao, Alejandro Flavio Gonzalez