Abstract: A more efficient method of counting the number of zeros in a 4-bit value generates three output bits (q0, q1 and q2) from four input bits (a0, a1, a2 and a3) according to the logic equations q0=not(a1+a2+a3+a4), q1=not(a0+a1), q2=a1(not a0)+not(a0+a2). These output bits yield the number of non-significant (leading or trailing) zeros in the 4-bit value. The invention may be implemented in a 16-bit zero counter having four 4-bit decoders, but is applicable to any number of zero counters. The output bits from the four 4-bit decoders can be combined to yield a 5-bit count whose most significant bit is a one when all input bits from all four of the 4-bit blocks are zero. A multiplexer stage derives two outputs based on a portion of the decode bits. For wider counters, the output stage uses four AOI21 gates to merge additional decode bits from a next lower 16-bit zero counter.

Abstract: Methods and apparatuses to measure temperatures of integrated circuits are disclosed. New circuit arrangements for measuring temperature using various types of integrated circuit sensor elements are discussed. Embodiments comprise methods and apparatuses arranged to measure temperature based upon current leakage rates of different integrated circuit sensor elements. The methods and apparatuses generally involve using a pulse module to generate a charge for the integrated circuit elements. In these method and apparatus embodiments, one or more elements form a decay module to sense when the voltage decays to a threshold value. The method and apparatus embodiments may also have a module to calculate or infer a temperature from the rate of the voltage decay.

Abstract: An eight-transistor tri-state driver. The tri-state driver implements multiple cascade structures where each cascade structure may refer to a pair of complementary transistors serially connected. Each cascade structure may include a p-conductivity type transistor serially connected to a n-conductivity type transistor. By implementing cascade structures in a tri-state driver, there is a lower peak current consumption, a reduced slew rate as well as a reduction in the amount of layout area used in comparison to the classic tri-state drivers.

Abstract: A more efficient method of counting the number of zeros in a 4-bit value generates three output bits (q0, q1 and q2) from four input bits (a0, a1, a2 and a3) according to the logic equations q0=not(a1+a2+a3+a4), q1=not(a0+a1), q2=a1(not a0)+not(a0+a2). These output bits yield the number of non-significant (leading or trailing) zeros in the 4-bit value. The invention may be implemented in a 16-bit zero counter having four 4-bit decoders, but is applicable to any number of zero counters. The output bits from the four 4-bit decoders can be combined to yield a 5-bit count whose most significant bit is a one when all input bits from all four of the 4-bit blocks are zero. A multiplexer stage derives two outputs based on a portion of the decode bits. For wider counters, the output stage uses four AOI21 gates to merge additional decode bits from a next lower 16-bit zero counter.

Abstract: A more efficient method of counting the number of zeros in a 4-bit value generates three output bits (q0, q1 and q2) from four input bits (a0, a1, a2 and a3) according to the logic equations q0=not(a1+a2+a3+a4), q1=not(a0+a1), q2=a1(not a0)+not(a0+a2). These output bits yield the number of non-significant (leading or trailing) zeros in the 4-bit value. The invention may be implemented in a 16-bit zero counter having four 4-bit decoders, but is applicable to any number of zero counters. The output bits from the four 4-bit decoders can be combined to yield a 5-bit count whose most significant bit is a one when all input bits from all four of the 4-bit blocks are zero. A multiplexer stage derives two outputs based on a portion of the decode bits. For wider counters, the output stage uses four AOI21 gates to merge additional decode bits from a next lower 16-bit zero counter.

Abstract: A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. The self-adaptive keeper utilizes a 2-stage embedded current mirror circuit, a dummy cell and a keeper transistor to compensate leakage current. The load impact of the self-adaptive keeper on the dynamic circuit components (for example, the impact on memory cells) is minimized by a dummy cell which detects and matches the instant leakage current. Amplification in the 2-stage embedded current mirror circuit provides an optimal current strength in the keeper transistor. The optimally amplified leakage current is utilized to compensate for a leakage induced voltage drop at the circuit's output. Thus, the self-adaptive keeper ensures the robustness of the circuit in real time and does not create any negative trade-off on read latency.

Abstract: A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. The self-adaptive keeper utilizes a 2-stage embedded current mirror circuit, a dummy cell and a keeper transistor to compensate leakage current. The load impact of the self-adaptive keeper on the dynamic circuit components (for example, the impact on memory cells) is minimized by a dummy cell which detects and matches the instant leakage current. Amplification in the 2-stage embedded current mirror circuit provides an optimal current strength in the keeper transistor. The optimally amplified leakage current is utilized to compensate for a leakage induced voltage drop at the circuit's output. Thus, the self-adaptive keeper ensures the robustness of the circuit in real time and does not create any negative trade-off on read latency.

Abstract: Methods and apparatuses to measure temperatures of integrated circuits are disclosed. New circuit arrangements for measuring temperature using various types of integrated circuit sensor elements are discussed. Embodiments comprise methods and apparatuses arranged to measure temperature based upon current leakage rates of different integrated circuit sensor elements. The methods and apparatuses generally involve using a pulse module to generate a charge for the integrated circuit elements. In these method and apparatus embodiments, one or more elements form a decay module to sense when the voltage decays to a threshold value. The method and apparatus embodiments may also have a module to calculate or infer a temperature from the rate of the voltage decay.

Abstract: A more efficient method of counting the number of zeros in a 4-bit value generates three output bits (q0, q1 and q2) from four input bits (a0, a1, a2 and a3) according to the logic equations q0=not(a1+a2+a3+a4), q1=not(a0+a1), q2=a1(not a0)+not(a0+a2). These output bits yield the number of non-significant (leading or trailing) zeros in the 4-bit value. The invention may be implemented in a 16-bit zero counter having four 4-bit decoders, but is applicable to any number of zero counters. The output bits from the four 4-bit decoders can be combined to yield a 5-bit count whose most significant bit is a one when all input bits from all four of the 4-bit blocks are zero. A multiplexer stage derives two outputs based on a portion of the decode bits. For wider counters, the output stage uses four AOI21 gates to merge additional decode bits from a next lower 16-bit zero counter.