Abstract: A circuit includes: first analog-to-digital converters (ADCs) configured to be coupled to respective ones of first sensors; a first multiplexer (MUX) coupled to output terminals of the first ADCs; a second MUX configured to be coupled to second sensors which are redundant sensors for the first sensors; a second ADC coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal; a first checker circuit configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches coupled between respective ones of the input terminals of the second MUX and a reference voltage node.

Abstract: A semiconductor device includes a semiconductor die having a vertical transistor device with a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and includes at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode, A second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: The present application relates to a semiconductor device, including: a field electrode in a needle-shaped field electrode trench extending from a frontside of a semiconductor body into the semiconductor body; a lower metallization layer on the frontside of the semiconductor body and electrically connected to the field electrode; an insulating layer on the lower metallization layer; an upper metallization layer on the insulating layer, and a first interconnect electrically connecting the lower metallization layer to the upper metallization layer. The first interconnect is laterally offset to the field electrode trench. The lower metallization layer is not connected to the upper metallization layer in a region vertically above the field electrode trench.

Abstract: A semiconductor die includes a semiconductor device and an edge termination structure laterally between the semiconductor device and a lateral edge of the die. The edge termination structure includes a first inner shield electrode region with a shield electrode in a trench extending into a semiconductor body, an outer shield electrode region with a shield electrode in a trench extending into the semiconductor body and disposed in a first lateral direction between the first inner shield electrode region and the lateral edge, and a well region formed in the semiconductor body adjacent the trench of the first inner shield electrode region. The shield electrode of the first inner shield electrode region is electrically connected to the well region to tap an electrical potential from the well region. The shield electrode of the outer shield electrode region is electrically connected to the shield electrode of the first inner shield electrode region.

Abstract: The disclosure relates to a semiconductor device having a first active region, a plurality of elongated gate regions having an elongated extension in a first lateral direction, respectively, a plurality of elongated field plate regions having an elongated extension in the first lateral direction, respectively, and a first additional gate region, wherein a first one of the elongated gate regions is arranged in a first elongated gate trench at a first side of the first active region, and a second one of the elongated gate regions is arranged in a second elongated gate trench at a second side of the first active region, the second side lying opposite to the first side with respect to a second lateral direction, and wherein the first additional gate region is arranged in a first additional gate trench which extends at least proportionately in the second lateral direction through the first active region.

Abstract: The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field including transistor cells, and an edge termination region laterally surrounding the cell field. Each transistor cell includes a drift region of a first conductivity type, a first body region of a second conductivity type on the drift region, a source region of the first conductivity type on the first body region and a gate electrode. The transistor device further includes an elongate source contact having opposing first and second distal ends, the elongate source contact being in contact with the source region, and a second body region of the second conductivity type positioned in the semiconductor substrate. The second body region has a lateral extent such that it is spaced part from the second distal end of the elongate source contact and extends laterally beyond the first distal end of the elongate source contact.

Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field, and an edge termination region laterally surrounding the cell field. The cell field includes elongate trenches that extend from the first major surface into the semiconductor substrate and that are positioned substantially parallel to one another such that one or more inner elongate trenches are arranged between two outermost elongate trenches and elongate mesas, each elongate mesa being formed between neighbouring elongate trenches. The elongate mesas include a drift region, a body region on the drift region and a source region on the body region. In a top view, one or both of the outermost elongate trenches has a different contour from the one or more inner elongate trenches.

Abstract: The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Abstract: The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region.

Abstract: In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode. A second metallization structure is located on the second surface and comprises a conductive structure and an electrically insulating layer and forms an outermost surface of the semiconductor device. The outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: The disclosure relates to a semiconductor device having a first active region, a plurality of elongated gate regions having an elongated extension in a first lateral direction, respectively, a plurality of elongated field plate regions having an elongated extension in the first lateral direction, respectively, and a first additional gate region, wherein a first one of the elongated gate regions is arranged in a first elongated gate trench at a first side of the first active region, and a second one of the elongated gate regions is arranged in a second elongated gate trench at a second side of the first active region, the second side lying opposite to the first side with respect to a second lateral direction, and wherein the first additional gate region is arranged in a first additional gate trench which extends at least proportionately in the second lateral direction through the first active region.

Abstract: A circuit for protecting a transistor is disclosed. The circuit includes a temperature sensing device coupled to the transistor and a tunable clamping circuit connected between transistor terminals, wherein the tunable clamping circuit is configured to provide an adjustable clamping voltage. A temperature controller coupled to the temperature sensing device and the tunable clamping circuit is also included. The temperature controller is configured to trigger a change in a clamping voltage of the tunable clamping circuit based on a feedback from the temperature sensing device.

Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

Abstract: A circuit for protecting a transistor is enclosed. The circuit includes a temperature sensing device coupled to the transistor and a tunable clamping circuit connected between transistor terminals, wherein the tunable clamping circuit is configured to provide an adjustable clamping voltage. A temperature controller coupled to the temperature sensing device and the tunable clamping circuit is also included. The temperature controller is configured to trigger a change in a clamping voltage of the tunable clamping circuit based on a feedback from the temperature sensing device.

Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

Abstract: The purpose of this invention is to connect electrical service wires from a main electrical feed 500 KCMIL cable to residential and commercial customers with #2 and #6 Service Cables. It will also expedite the restoration of Electric Service to the customer, by eliminating multiple Crab Joints.