Patents by Inventor Alessandro Magnavacca
Alessandro Magnavacca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230376230Abstract: A memory device may include a plurality of non-volatile memory devices and a controller. The controller may be configured to generate first parity data for a portion of a data block stored in a plurality of memory blocks of the plurality of non-volatile memory devices, store the first parity data in a swap block that includes one or more non-volatile memory devices of the plurality of non-volatile memory devices, generate second parity data for the data block, store the second parity data in the swap block, perform a partial read back of the data block, store, after performing the partial read back, the second parity data in a subset of the plurality of memory blocks, and release the first parity data from the swap block after storing the second parity data in the subset of the plurality of memory blocks.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Inventor: Alessandro MAGNAVACCA
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Patent number: 11670342Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.Type: GrantFiled: December 24, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
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Patent number: 11657878Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.Type: GrantFiled: January 27, 2022Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Pollio, Giuseppe Vito Portacci, Mauro Luigi Sali, Alessandro Magnavacca
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Publication number: 20220223211Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.Type: ApplicationFiled: January 27, 2022Publication date: July 14, 2022Inventors: Antonino Pollio, Giuseppe Vito Portacci, Mauro Luigi Sali, Alessandro Magnavacca
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Publication number: 20220189513Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of ones stored in the first physical page.Type: ApplicationFiled: December 24, 2021Publication date: June 16, 2022Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
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Patent number: 11238940Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.Type: GrantFiled: November 19, 2020Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Antonino Pollio, Giuseppe Vito Portacci, Mauro Luigi Sali, Alessandro Magnavacca
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Patent number: 11211100Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: GrantFiled: December 15, 2020Date of Patent: December 28, 2021Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
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Publication number: 20210098030Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: ApplicationFiled: December 15, 2020Publication date: April 1, 2021Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
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Patent number: 10872639Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: GrantFiled: August 29, 2019Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
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Publication number: 20200211603Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.Type: ApplicationFiled: August 29, 2019Publication date: July 2, 2020Inventors: Xiangang Luo, Jianmin Huang, Patroclo Fumagalli, Scott Anthony Stoller, Alessandro Magnavacca, Andrea Pozzato
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Patent number: 7710772Abstract: A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.Type: GrantFiled: April 25, 2008Date of Patent: May 4, 2010Inventors: Alessandro Magnavacca, Francesco Pipitone, Carlo Lisi, Antonio Geraci
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Patent number: 7596023Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: GrantFiled: November 2, 2007Date of Patent: September 29, 2009Inventors: Alessandro Magnavacca, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Publication number: 20080266946Abstract: A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.Type: ApplicationFiled: April 25, 2008Publication date: October 30, 2008Applicant: STMicroelectronics S.r.I.Inventors: Alessandro Magnavacca, Francesco Pipitone, Carlo Lisi, Antonino Geraci
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Publication number: 20080106937Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: ApplicationFiled: November 2, 2007Publication date: May 8, 2008Applicant: STMicroelectronics S.r.I.Inventors: Alessandro MAGNAVACCA, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Patent number: 6950324Abstract: The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.Type: GrantFiled: December 3, 2003Date of Patent: September 27, 2005Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Magnavacca, Andrea Bellini, Francesco Mastroiani, Marco Defendi
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Patent number: 6950337Abstract: A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.Type: GrantFiled: November 21, 2003Date of Patent: September 27, 2005Assignee: STMicroelectronics S.r.l.Inventors: Andrea Bellini, Mauro Sali, Alessandro Magnavacca, Carlo Lisi
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Publication number: 20040156235Abstract: A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.Type: ApplicationFiled: November 21, 2003Publication date: August 12, 2004Applicant: STMicroelectronics S.r.I.Inventors: Andrea Bellini, Mauro Sali, Alessandro Magnavacca, Carlo Lisi
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Publication number: 20040136218Abstract: The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.Type: ApplicationFiled: December 3, 2003Publication date: July 15, 2004Applicant: STMicroelectronics S.r.l.Inventors: Alessandro Magnavacca, Andrea Bellini, Francesco Mastroianni, Marco Defendi