Patents by Inventor Alessandro Minzoni
Alessandro Minzoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887974Abstract: A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.Type: GrantFiled: February 2, 2022Date of Patent: January 30, 2024Assignee: AP Memory Technology Corp.Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
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Patent number: 11757432Abstract: A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.Type: GrantFiled: March 17, 2022Date of Patent: September 12, 2023Assignee: AP Memory Technology (Hangzhou) Limited CoInventors: Xuan Zhang, Po Han Chen, Keng Lone Wong, Alessandro Minzoni
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Publication number: 20220302905Abstract: A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.Type: ApplicationFiled: March 17, 2022Publication date: September 22, 2022Applicant: AP Memory Technology (Hangzhou) Limited CoInventors: Xuan ZHANG, Po Han CHEN, Keng Lone WONG, Alessandro MINZONI
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Publication number: 20220157800Abstract: A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.Type: ApplicationFiled: February 2, 2022Publication date: May 19, 2022Applicant: AP Memory Technology Corp.Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
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Patent number: 11315916Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.Type: GrantFiled: September 13, 2020Date of Patent: April 26, 2022Assignee: AP Memory Technology Corp.Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
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Patent number: 10949294Abstract: A method of correcting an error in a memory array in a DRAM during a read operation, wherein the memory array includes a data array and an ECC array, the method comprising: reading data from the memory array; when the data contains one or more erroneous data bits, correcting the erroneous data bits by an ECC decoding and correcting module in the DRAM; registering only corrected erroneous data bits and their positions in a register; controlling a plurality of write drivers in the DRAM by the register so as to write only the corrected erroneous data bits back to the memory array.Type: GrantFiled: May 17, 2018Date of Patent: March 16, 2021Assignee: Xi'an UNIIC Semiconductors Co., Ltd.Inventor: Alessandro Minzoni
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Publication number: 20200411497Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.Type: ApplicationFiled: September 13, 2020Publication date: December 31, 2020Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
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Publication number: 20200364547Abstract: The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.Type: ApplicationFiled: April 17, 2020Publication date: November 19, 2020Applicants: ICLEAGUE Technology Co., Ltd., AP Memory Technology Corp.Inventors: Wenliang CHEN, Eugene Jinglun TAM, Lin MA, Joseph Zhifeng XIE, Alessandro MINZONI
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Patent number: 10811402Abstract: The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.Type: GrantFiled: December 26, 2018Date of Patent: October 20, 2020Assignee: AP Memory Technology Corp.Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
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Patent number: 10769012Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, a flag bit array, an ECC encoding module, an ECC decoding module, a flag bit generation module and a flag bit detection module; wherein: the flag bit generation module is configured, when data is being written, to generate a flag bit and an encode enable signal, the flag bit being stored in the flag bit array, and the encode enable signal being used to control the operation of the ECC encoding module; the ECC encoding module is configured to encode the data to be written according to the ECC algorithm preset therein so as to generate parity bits; the ECC array is configured to store the generated parity bits; the flag bit detection module is configured, when data is being read, to detect the flag bit and control the operation of the ECC decoding module; and the ECC decoding module is configured to detect and correct erroneous data using the parity bits from the ECC array and the data from the dataType: GrantFiled: May 17, 2018Date of Patent: September 8, 2020Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.Inventor: Alessandro Minzoni
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Publication number: 20200212027Abstract: The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.Type: ApplicationFiled: December 26, 2018Publication date: July 2, 2020Inventors: WENLIANG CHEN, LIN MA, ALESSANDRO MINZONI
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Patent number: 10665317Abstract: A method of ECC encoding a DRAM and a DRAM thereof. The method comprises determining whether to encode the data according to the value of a flag bit while the DRAM is being refreshed. The ECC encoding module encodes data only if of the flag bit setting and detecting module generates an enable signal. As a result, the length of the valid data for ECC encoding can be guaranteed to comply with the requirements of ECC encoding.Type: GrantFiled: May 17, 2018Date of Patent: May 26, 2020Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.Inventor: Alessandro Minzoni
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Publication number: 20180336091Abstract: The present invention relates to a method of correcting an error in a memory array in a DRAM during a read operation, wherein the memory array includes a data array and an ECC array, the method comprising: reading data from the memory array; when the data contains one or more erroneous data bits, correcting the erroneous data bits by an ECC decoding and correcting module in the DRAM; registering only corrected erroneous data bits and their positions in a register; controlling a plurality of write drivers in the DRAM by the register so as to write only the corrected erroneous data bits back to the memory array. The invention also relates to a DRAM.Type: ApplicationFiled: May 17, 2018Publication date: November 22, 2018Inventor: Alessandro Minzoni
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Publication number: 20180336090Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, a flag bit array, an ECC encoding module, an ECC decoding module, a flag bit generation module and a flag bit detection module; wherein: the flag bit generation module is configured, when data is being written, to generate a flag bit and an encode enable signal, the flag bit being stored in the flag bit array, and the encode enable signal being used to control the operation of the ECC encoding module; the ECC encoding module is configured to encode the data to be written according to the ECC algorithm preset therein so as to generate parity bits; the ECC array is configured to store the generated parity bits; the flag bit detection module is configured, when data is being read, to detect the flag bit and control the operation of the ECC decoding module; and the ECC decoding module is configured to detect and correct erroneous data using the parity bits from the ECC array and the data from the dataType: ApplicationFiled: May 17, 2018Publication date: November 22, 2018Inventor: Alessandro Minzoni
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Publication number: 20180336959Abstract: The present invention relates to a method of ECC encoding a DRAM and a DRAM. The method comprises determining whether to encode the data according to the value of a flag bit while the DRAM is being refreshed. The ECC encoding module encodes data only of the flag bit setting and detecting module generates an enable signal. The advantage of the method is that the length of the valid data for ECC encoding can be guaranteed to comply with the requirements of ECC encoding.Type: ApplicationFiled: May 17, 2018Publication date: November 22, 2018Inventor: Alessandro Minzoni
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Patent number: 9652323Abstract: A computer memory access method includes: receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion; writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit and reading a third data portion corresponding to the masked second data portion from the data storage unit by a reading unit; producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion; generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then writing the parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit.Type: GrantFiled: October 30, 2014Date of Patent: May 16, 2017Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.Inventors: Alessandro Minzoni, Ni Fu
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Patent number: 9524209Abstract: A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.Type: GrantFiled: October 30, 2014Date of Patent: December 20, 2016Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.Inventors: Alessandro Minzoni, Ni Fu
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Patent number: 9361180Abstract: Methods, systems and apparatus for storing data by an ECC memory are provided. In one aspect, when an ECC memory configured to be used for data blocks with a first data length is used for data blocks with a reduced second data length, a method includes storing at least one data block with the second data length in a data bit storage part of a storage array and storing parity bits generated for only one data block of the at least one data block according to a relevant encoding rule in a parity bit storage part of the storage array. When the at least one data block is two or more data blocks, one or more judgment bits, which indicate that the stored parity bits correspond to the only one data block, are stored in one or more storage bits of the parity bit storage part that are not occupied.Type: GrantFiled: October 30, 2014Date of Patent: June 7, 2016Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.Inventors: Alessandro Minzoni, Ni Fu
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Publication number: 20160124803Abstract: Methods, devices, and systems for storage device data access and/or storage device error correction are provided. In one aspect, a storage device data access method comprises generating a parity bit for data to be stored; generating a flag bit that expresses whether a data mask is present or absent in the data to be stored; storing the data, the flag bit, and the parity bit; reading out the data, the flag bit and the parity bit; determining whether the data mask is present or absent based on the read out flag bit; in response to determining that the flag bit expresses the absence of the data mask, detecting and correcting the data using the read out parity bit; otherwise, in response to determining that the flag bit expresses the presence of the data mask, performing no detection or correction on the data.Type: ApplicationFiled: March 19, 2014Publication date: May 5, 2016Inventor: Alessandro MINZONI
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Publication number: 20150121172Abstract: A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.Type: ApplicationFiled: October 30, 2014Publication date: April 30, 2015Inventors: Alessandro MINZONI, Ni FU