Abstract: A CAM memory is supplied targeted at storing data words whose bits can take on an indifferent logical value besides two complementary logical values. it includes a matrix (MA) of memory cells in which a pair of cells is assigned to each bit that can take on a ternary configuration. circuits (CT1 . . . CT3, WR, SR; CT11 . . . SR1, CT21 . . . SR2) for memory (MA) matrix access control give access for performing comparisons during operation in the CAM mode or for writing/reading data by means of direct RAM mode addressing (FIG. 1).

Abstract: The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1 . . . IMn) which is arranged to perform either the function of determining motion vectors and associated costs for different prediction modes, or the function of vector refinement, possibly in addition to prediction mode selection. The circuit (IM) is based on the use of two operating units (M1, M2) which are arranged to concurrently process in different ways different pixel groups according to a MIMD technique. Preferably, when the circuit performs motion vector determination, the operating units (M1, M2) are programmed to execute a genetic algorithm exploiting an initial vector population taking into account the temporal and spatial correlations in the picture.

Abstract: The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the second consists of a 4-transistor series cirucit, two P-MOS (T3, T4) and two N-MOS (T5, T6) geenrating carry output CoutN complemented when the two operands have equal logic levels.

Abstract: The arithmetic-logic unit has elementary cells performing logic addition, one for each pair of operand bits, which are particularly optimized as far as carry propogation speed is concerned and are controlled by an auxiliary fast logic allowing their performance to be extended to the other operations. The unit also has a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell.

Abstract: The circuit comprises two registers (SR12, SR8) which temporarily memorize uncompressed and compressed PCM words, respectively. The uncompressed word is sequentially read and a counter (CNT) counts the number of zeroes present in the most significant positions of the absolute value of the word. The compressed word is composed, in the corresponding register, of the sign bit of the uncompressed word, followed by the counting bits of the counter and by the bits of the positions of the uncompressed word following those of the counted zeroes.