Abstract: A method for clustering nucleotide strings of DNA strand replicas in clusters, comprising, for each pair of a first nucleotide string and a second nucleotide string, carrying out: arranging a matrix wherein each matrix element corresponds to a selected nucleotide in the first nucleotide string and to a further selected nucleotide in the second nucleotide string and is configured to store a calculated edit value indicative of an edit distance; progressively filling the matrix by storing calculated edit values; if the edit value calculated for a matrix element belonging to an output diagonal of the matrix is not lower than a cluster threshold, stopping said progressively filling and placing said first and second nucleotide strings in two different clusters, said output diagonal comprising the matrix element corresponding to the last column and the last row of the matrix.

Abstract: A method and associated system for randomizing data to be stored in a memory storage device including, receiving a plurality of data bytes to be randomized at a memory controller and written to a page of a memory storage device, wherein the page comprises a plurality of data sectors and wherein each of the plurality of data sectors are configured to store a plurality of data bytes, randomizing a first portion of the plurality of data bytes using a first randomizer initialized by a first seed to generate a first portion of randomized data bytes and randomizing a second portion of the plurality of data bytes using a second randomizer initialized by a second seed to generate a second portion of randomized data bytes, wherein the first seed is uncorrelated with the second seed.

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the 5 transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for assuring retention are disclosed. The nonvolatile memory controller includes a retention monitor that stores test characteristics corresponding to a use case and determines, each time that a read of a codeword is performed, whether the number of errors in the codeword exceed a retention threshold. If the number of errors in the codeword exceed the retention threshold, the block containing the codeword is retired. The retention monitor performs retention tests during the operation of the memory controller and adjusts the retention threshold when the results of the retention tests indicate deviation from the test characteristics corresponding to a use case.

Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values.

Abstract: Methods and apparatus are disclosed for decoding low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers. The apparatus includes a decoder having circuitry to decode, layer by layer, a LDPC codeword utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword, the functional adjustments including layer specific parameters for at least two layers of the parity check matrix associated with the LDPC codeword.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

Abstract: A method and associated system for randomizing data to be stored in a memory storage device including, receiving a plurality of data bytes to be randomized at a memory controller and written to a page of a memory storage device, wherein the page comprises a plurality of data sectors and wherein each of the plurality of data sectors are configured to store a plurality of data bytes, randomizing a first portion of the plurality of data bytes using a first randomizer initialized by a first seed to generate a first portion of randomized data bytes and randomizing a second portion of the plurality of data bytes using a second randomizer initialized by a second seed to generate a second portion of randomized data bytes, wherein the first seed is uncorrelated with the second seed.

Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

Abstract: A method to decode low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers, includes receiving a plurality of values at a decoder. Each value of the plurality of values represents one of a plurality of bits of an LDPC codeword encoded using the parity check matrix. The LDPC codeword is decoded using layered scheduling. A functional adjustment is applied to an approximation of belief propagation used during the decoding. At least one layer specific functional adjustment is used to provide an estimate of the codeword. An apparatus to decode low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers includes a decoder. The decoder includes circuitry to decode, layer by layer, the LDPC encoded data utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory controller includes a storage module configured to store data indicating threshold voltage shift read parameters and corresponding index values. The nonvolatile memory controller includes a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device, and a read circuit configured to determine whether a usage characteristic meets a usage characteristic threshold. When a usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent reads of the nonvolatile memory device using a threshold voltage shift read instruction identified using one or more of the threshold voltage shift read parameters.

Abstract: A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

Abstract: A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

Abstract: A nonvolatile memory controller includes memory storage configured to store a two-index look-up table that includes a Log-Likelihood Ratio (LLR), hard-and-soft-decision bits associate with the LLR and a neighboring cell read pattern associated with the LLR. Read circuitry is configured to perform a plurality of reads of a cell of a nonvolatile memory storage module at different read voltage levels to generate target cell hard-and-soft-decision bits and configured to read neighboring cells to generate neighboring cell reads. Neighboring cell processing circuitry combines the neighboring cell reads to generate a neighboring cell read pattern. Look-up circuitry accesses the two-index look-up table using the target cell hard-and-soft-decision bits and the neighboring cell read pattern to identify the corresponding LLR for use in Low-Density Parity Check (LDPC) decoding of a codeword stored in the nonvolatile memory storage module.

Abstract: An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.

Abstract: A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools.

Abstract: A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of the memory storage module, wherein each of the plurality of lifetime specific LLR look-up tables comprises a plurality of LLRs representative of a specific point in the lifetime of the memory storage module for each of the plurality of soft-decision bits. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.