Patents by Inventor Alex E. Henderson
Alex E. Henderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11108591Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.Type: GrantFiled: March 18, 2014Date of Patent: August 31, 2021Inventors: Alex E. Henderson, Walter E. Croft, John W Hayes, Linda Elaine Eaton Hayes
-
Publication number: 20160226756Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.Type: ApplicationFiled: March 18, 2014Publication date: August 4, 2016Inventors: Alex E. Henderson, Walter E. Croft, John William Hayes, Linda Elaine Eaton Hayes
-
Patent number: 8547843Abstract: A system, method and computer program product are provided. In use, a plurality of flows associated with packets destined for an output port is identified. A utilization associated with the output port is further measured. Thus, rates of a plurality of the flows destined for the output port may be individually controlled at an input port thereof, based on the utilization to ensure that the utilization remains less than 99.9% and avoid buffering more than 400 packets with a correspondingly low delay.Type: GrantFiled: January 20, 2006Date of Patent: October 1, 2013Assignee: Saisei Networks Pte LtdInventors: Lawrence G. Roberts, Alex E. Henderson
-
Publication number: 20130208732Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.Type: ApplicationFiled: February 15, 2012Publication date: August 15, 2013Inventors: Alex E. Henderson, John William Hayes, Linda Elaine Eaton Hayes, Walter E. Croft
-
Publication number: 20100208730Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.Type: ApplicationFiled: February 17, 2009Publication date: August 19, 2010Inventors: Alex E. Henderson, John William Hayes, Linda Elaine Eaton Hayes, Walter E. Croft
-
Publication number: 20090034522Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows Ethernet equipment to be placed into service as SAN components.Type: ApplicationFiled: August 3, 2007Publication date: February 5, 2009Inventors: John William Hayes, Linda Elaine Eaton Hayes, Walter E. Croft, Alex E. Henderson
-
Patent number: 7333502Abstract: In a services processor, a queue operations unit controls the output of processed data packets from the services processor. In accordance with a hybrid list/calendar queue priority scheme, the queue operations unit uses a unique data structure comprising a tree of calendar arrays and queue lists to schedule the data packets for output.Type: GrantFiled: February 4, 2003Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Patent number: 7333484Abstract: A services processor includes an editing unit, which performs various functions for editing data packets, such as packet creation, packet encapsulation, and packet replication.Type: GrantFiled: February 4, 2003Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Patent number: 7333490Abstract: The invention provides apparati and methods for processing a packet. The processing is done according to a table and context based scheme.Type: GrantFiled: February 4, 2003Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Publication number: 20080028096Abstract: Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.Type: ApplicationFiled: October 21, 2003Publication date: January 31, 2008Inventors: Alex E. Henderson, John William Hayes, Walter E. Croft, Linda Elaine Eaton
-
Patent number: 7307986Abstract: The invention provides apparatuses and methods for quickly modifying state information. Preprocessing prepares the state information to be modified. A logic unit modifies the state information. Postprocessing then puts the modified state information in proper form for output.Type: GrantFiled: February 4, 2003Date of Patent: December 11, 2007Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Patent number: 7133400Abstract: A system for filtering data comprises a filtering database for storing layered rule tables and a data filtering engine coupled to the filtering database for filtering the input data using the layered rule tables. The data filtering engine filters or classifies input data using tests or rules performed on the data elements in the input data. The data elements are segments of data in the input data and are selected from the input data using a data element locator. Preferably, each rule table in the filtering database comprises a data element locator, a default rule, and zero or more filtering rules. The filtering rules comprise the tests or rules that are to be applied to the data elements. Each rule table corresponds to a single data element and each filtering rule in the rule table is to be applied to that data element.Type: GrantFiled: January 29, 1999Date of Patent: November 7, 2006Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Patent number: 7058789Abstract: A network services processor receives, stores, and modifies incoming packets and transmits them to their intended destination. The network services processor stores packets as buffers in main and cache memory for manipulation and retrieval. A memory subsystem stores packets as linked lists of buffers. Each bank of memory includes a separate memory management controller for controlling accesses to the memory bank. The memory management controllers, a cache management unit, and free list manager shift the scheduling of read and write operations to maximize overall system throughput. For each packet, packet context registers are assigned, including a packet handle that points to the location in memory of the packet buffer. The contents of individual packets can be accessed through the use of encapsulation pointer registers that are directed towards particular offsets within a packet, such as the beginning of different protocol layers within the packet.Type: GrantFiled: February 4, 2003Date of Patent: June 6, 2006Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Patent number: 7013367Abstract: An apparatus and method for caching data in an associative memory cache using a single non-overlapping entry, wherein the non-overlapping entry is created from a matching entry and one or more overlapping entries that are stored in a primary associative memory.Type: GrantFiled: July 17, 2003Date of Patent: March 14, 2006Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Publication number: 20040133590Abstract: A tree data structure with range-specifying keys and associated methods. In one embodiment, the data structure is a tree that is stored in a machine readable medium. Each key has two values that define a range and has an associated data item that is associated with the range. Various embodiments of processes to search the tree, add ranges and keys to the tree, delete ranges and keys from the tree, and to generally maintain the tree data structure are disclosed.Type: ApplicationFiled: August 8, 2003Publication date: July 8, 2004Inventors: Alex E. Henderson, Laxminarayana Tumuluru, Monis Rahman, Richard D. Trauben
-
Patent number: 6748484Abstract: A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data item stored in the associative memory. The priority field corresponds to criteria that is used to order the priority of the data items in the associative memory. A match resolution circuit is coupled to receive match signals from an associative memory, such as a CAM, and the priority fields of the matching data items. The match resolution structure compares the priority fields of the matching data items to determine which data item has the highest priority. The match resolution structure indicates the data item with the highest priority in the priority field as the best match of the associative memory for the particular search input.Type: GrantFiled: August 10, 2000Date of Patent: June 8, 2004Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft, Raymond M. Chu, Vishal Sarin
-
Publication number: 20040078516Abstract: An apparatus and method for caching data in an associative memory cache using a single non-overlapping entry, wherein the non-overlapping entry is created from a matching entry and one or more overlapping entries that are stored in a primary associative memory.Type: ApplicationFiled: July 17, 2003Publication date: April 22, 2004Inventors: Alex E. Henderson, Walter E. Croft
-
Patent number: 6721842Abstract: A boundary addressable memory (BAM) array comprises a plurality of BAM word modules, each BAM word module comprises a plurality of BAM cells for performing arithmetic comparisons between input data and an upper bound value and a lower bound value stored in each BAM cell to generate a matching signal indicating whether the input data is not greater than the upper bound value and not less than the lower bound value or whether the input data is not greater than the lower bound value and not less than the upper bound value.Type: GrantFiled: November 7, 2001Date of Patent: April 13, 2004Assignee: Intel CorporationInventors: Alex E. Henderson, Walter E. Croft
-
Publication number: 20040042490Abstract: The invention provides apparati and methods for quickly modifying state information. Preprocessing prepares the state information to be modified. A logic unit modifies the state information. Postprocessing then puts the modified state information in proper form for output.Type: ApplicationFiled: February 4, 2003Publication date: March 4, 2004Inventors: Alex E. Henderson, Walter E. Croft
-
Publication number: 20040037276Abstract: A network services processor receives, stores, and modifies incoming packets and transmits them to their intended destination. The network services processor stores packets as buffers in main and cache memory for manipulation and retrieval. A memory subsystem stores packets as linked lists of buffers. Each bank of memory includes a separate memory management controller for controlling accesses to the memory bank. The memory management controllers, a cache management unit, and free list manager shift the scheduling of read and write operations to maximize overall system throughput. For each packet, packet context registers are assigned, including a packet handle that points to the location in memory of the packet buffer. The contents of individual packets can be accessed through the use of encapsulation pointer registers that are directed towards particular offsets within a packet, such as the beginning of different protocol layers within the packet.Type: ApplicationFiled: February 4, 2003Publication date: February 26, 2004Inventors: Alex E. Henderson, Walter E. Croft