Patents by Inventor Alex Joo

Alex Joo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay-locked loop and electronic device including the same
    Patent number: 8283958
    Abstract: A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Ryun Choi, Dong Hwan Lee, Su Ho Kim, Won Lee, Alex Joo, Ji Hun Oh
  • Delay locked loop, electronic device including the same, and method of operating the same
    Patent number: 8049543
    Abstract: A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: November 1, 2011
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hee Chai Kang, Kyeong Ho Ryu, Seong Ook Jung, Won Lee, Dong Hwan Lee, Alex Joo, Jong-Ryun Choi
  • Duty cycle correction circuits having short locking times that are relatively insensitive to temperature changes
    Patent number: 7990195
    Abstract: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: August 2, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Harmendra Panditd, Su Ho Kim, Won Lee, Alex Joo, Kwan Yeob Chae, Jong-Ryun Choi
  • Delay-locked loop and electronic device including the same
    Publication number: 20100219867
    Abstract: A delay locked loop is provided. The delay locked loop controls the number of delay cells that delay the phase of an input clock during a locking operation and controls a phase delay value of at least one delay cell among a plurality of delay cells after the locking operation is completed.
    Type: Application
    Filed: February 23, 2010
    Publication date: September 2, 2010
    Inventors: Jong-Ryun Choi, Dong Hwan Lee, Su Ho Kim, Won Lee, Alex Joo, Ji Hun Oh
  • Delay locked loop, electronic device including the same, and method of operating the same
    Publication number: 20100194456
    Abstract: A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
    Type: Application
    Filed: December 2, 2009
    Publication date: August 5, 2010
    Applicants: Industry-Academic Cooperation Foundation, Yonsei University, Samsung Electronics Co., Ltd.
    Inventors: Hee Chai Kang, Kyeong Ho Ryu, Seong Ook Jung, Won Lee, Dong Hwan Lee, Alex Joo, Jong Ryun Choi
  • DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES
    Publication number: 20100097112
    Abstract: A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal.
    Type: Application
    Filed: October 22, 2009
    Publication date: April 22, 2010
    Inventors: Harmendra Panditd, Su Ho Kim, Won Lee, Alex Joo, Kwan Yeob Chae, Jong-Ryun Choi