Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Abstract: A computer-implemented method of ensuring integrity of an integrated circuit (IC) is provided. The computer-implemented method includes providing a design layer that meets design rule checks (DRCs), identifying a first critical dimension (CD) distribution of the design layer and using retargeting shapes in the design layer to enable a biasing of CDs of targets to enable a provision of two different CD distributions, which are DRC clean and which are separate from one another and which cannot be expressed by a single Gaussian distribution.

Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.

Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.

Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

Abstract: Provided are embodiments for an MOL interconnect structure having low metal-to-metal interface resistance interconnect structure including one or more contacts of one or more devices formed on a substrate. A dielectric layer is formed on one or more devices. One or more trenches are formed in the dielectric layer. The MOL interconnect structure also includes a barrier layer formed on one or more portions of the dielectric layer, along with a metallization layer, wherein the metallization layer forms a metal-to-metal interface with the one or more contacts.