Abstract: A fast frame buffer system and architecture supports preferably 24-bit capability and includes an integer rendering pipeline, especially useful for three-dimensional applications. The system includes a frame buffer random access memory system ("FBRAM") that includes video source data and is configurable as a single-buffer or double-buffer, a fast frame buffer controller integrated circuit ("FFB ASIC") that includes system command and video refresh control functions, and a random access memory digital-to-analog converter unit ("RAMDAC") that includes the buffer system timing generator. A FBRAM controller unit provides both parallel accelerated rendering pipeline and direct access paths to the FBRAM unit. The timing generator outputs serial clock and serial clock enable signals, the latter signal preceding horizontal blanking signals by preferably N=1 serial clock pulses to compensate for pixel signal path timing delays.

Abstract: A frame buffer system is disclosed that employs non overlapping serial enable signals to access pixel data values from sets of pixel buffers contained in each interleave of a multiple interleave frame buffer according to the attribute data in the frame buffer. The frame buffer system provides circuitry for varying the interleave factor between frame buffer accesses and the generation of corresponding video data. The frame buffer system also provides circuitry for expanding double buffered pixel data values into full addressing for color look-up.