Patents by Inventor Alexander A. Demkov
Alexander A. Demkov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230132224Abstract: Electro-optic modulators and related devices and methods. The method includes forming a silicon dioxide layer on a silicon substrate. The method includes forming a doped silicon layer in or on the silicon dioxide layer. The method includes forming alternating layers of functional transition metal oxides (TMOs) on the doped silicon layer. Design parameters can be optimized to create realizable devices that minimize the energy consumption of, for example, a SrTiO3/LaAlO3 electro-optic modulator while maximizing electro-optic performance (e.g., modulation energies on the order of tens of pJ/bit).Type: ApplicationFiled: March 8, 2021Publication date: April 27, 2023Inventors: Alexander A. Demkov, John Elliott Ortmann, Jr., Agham Posadas
-
Patent number: 11561421Abstract: Various embodiments of the present technology enable growth of a-axis oriented barium titanate (BTO) films by inserting a relaxed strain control layer having a larger lattice constant than the c-axis of BTO and a similar thermal expansion mismatch. As a result, in-plane tensile stress causes BTO to grow with its ferroelectric polarization in-plane. Some embodiments allow for BTO films to immediately be grown on silicon with a-axis orientation, and without the need to create thick layers for relaxation. Using various embodiments of the present technology, the BTO can be grown in-plane with minimal dislocation density that is confined to the interface region.Type: GrantFiled: June 25, 2020Date of Patent: January 24, 2023Assignee: Board of Regents, The University of Texas SystemInventors: Alexander A. Demkov, Marc Reynaud, Agham Posadas
-
Publication number: 20220268996Abstract: Various embodiments provide for systems and techniques for the successful fabrication of metal oxide (TMO)-on-glass layer stacks via direct deposition. The resulting samples feature epitaxial, strontium titanate (STO) or barium titanate (BTO) films on silicon dioxide (SiO2) layers, forming STO- or BTO-buffered SiO2 pseudo-substrates. As the integration of TMO films on silicon rely on an STO or BTO buffer layer, a wide variety of TMO-based integrated devices (e.g., circuits, waveguides, etc.) can be fabricated from the TMO-on-glass platform of the present technology. Moreover, the STO, or the BTO, survives the fabrication process without a corresponding degradation of crystalline quality, as evidenced by various objective measures.Type: ApplicationFiled: April 29, 2022Publication date: August 25, 2022Inventors: Alexander A. Demkov, John Elliott Ortmann, Agham Posadas
-
Publication number: 20220130866Abstract: Some embodiments of the present technology simplify the process of producing SOI wafers significantly compared to traditional methods. Furthermore, various embodiments provide a route for the integration of perovskite transition metal oxide thin films with different properties into SOI wafers. As such films display a wide array of novel electronic, magnetic, and optical phenomena, their integration into technologically-relevant SOI wafers will likely allow for the construction of a wide array of novel devices.Type: ApplicationFiled: March 4, 2020Publication date: April 28, 2022Inventors: Alexander A. Demkov, J. Elliott Ortmann, Agham Posadas
-
Publication number: 20200409190Abstract: Various embodiments of the present technology enable growth of a-axis oriented barium titanate (BTO) films by inserting a relaxed strain control layer having a larger lattice constant than the c-axis of BTO and a similar thermal expansion mismatch. As a result, in-plane tensile stress causes BTO to grow with its ferroelectric polarization in-plane. Some embodiments allow for BTO films to immediately be grown on silicon with a-axis orientation, and without the need to create thick layers for relaxation. Using various embodiments of the present technology, the BTO can be grown in-plane with minimal dislocation density that is confined to the interface region.Type: ApplicationFiled: June 25, 2020Publication date: December 31, 2020Inventors: Alexander A. Demkov, Marc Reynaud, Agham Posadas
-
Patent number: 9293697Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.Type: GrantFiled: March 6, 2015Date of Patent: March 22, 2016Assignee: Board of Regents, The University of Texas SystemInventors: Alexander A. Demkov, Agham-Bayan S. Posadas
-
Publication number: 20150333253Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.Type: ApplicationFiled: March 6, 2015Publication date: November 19, 2015Inventors: Alexander A. Demkov, Agham-Bayan S. Posadas
-
Patent number: 9023662Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.Type: GrantFiled: May 7, 2012Date of Patent: May 5, 2015Assignee: Board of Regents, The University of Texas SystemInventors: Alexander A. Demkov, Agham-Bayan S. Posadas
-
Publication number: 20120286383Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.Type: ApplicationFiled: May 7, 2012Publication date: November 15, 2012Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Alexander A. Demkov, Agham-Bayan S. Posadas
-
Patent number: 7365410Abstract: A method for forming a semiconductor structure including providing a semiconductor substrate, forming a metallic buffer layer over the semiconductor substrate, forming an amorphous semiconductor layer over the metallic buffer layer, and recrystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer. A semiconductor structure includes a semiconductor substrate, a buffer layer comprising at least one of silicide and germanide formed over the semiconductor substrate, and a crystalline semiconductor layer formed over the metallic buffer layer.Type: GrantFiled: October 29, 2004Date of Patent: April 29, 2008Assignee: Freescale, Semiconductor, Inc.Inventors: Alexander A. Demkov, William J. Taylor, Jr.
-
Publication number: 20070218640Abstract: A semiconductor device having a gate with a thin conductive layer is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer, quantum confinement of carriers within conductive layer can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane from the Fermi level. Thus, the undesirable leakage current in the device can be reduced. Additional conductive layers may be used to provide more carriers.Type: ApplicationFiled: May 23, 2007Publication date: September 20, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Sinan Goktepeli, Alexander Demkov, Marius Orlowski
-
Patent number: 7235847Abstract: A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.Type: GrantFiled: September 17, 2004Date of Patent: June 26, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Sinan Goktepeli, Alexander A. Demkov, Marius K. Orlowski
-
Patent number: 7141857Abstract: Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series metal-containing dopant is comprised within the amorphous layer of hafnium oxide. The process comprises growing an amorphous layer of hafnium oxide overlying a substrate. The amorphous layer of hafnium oxide is doped with a dopant having the chemical formulation LnOx, where Ln is lanthanum, a lanthanide-series metal, or a combination thereof, and X is any number greater than zero. The doping step may be performed during or after growth of the amorphous layer of hafnium oxide.Type: GrantFiled: June 30, 2004Date of Patent: November 28, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Zhiyi Yu, Jay A. Curless, Yong Liang, Alexandra Navrotsky, Sergey Ushakov, Bich-Yen Nguyen, Alexander Demkov
-
Patent number: 7091568Abstract: A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO2)(1-x)(ZrO2)x, wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.Type: GrantFiled: December 22, 2004Date of Patent: August 15, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Rama I. Hegde, Alexander A. Demkov, Philip J. Tobin, Dina H. Triyoso
-
Publication number: 20060131671Abstract: A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO2)(1-x)(ZrO2)x, wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.Type: ApplicationFiled: December 22, 2004Publication date: June 22, 2006Inventors: Rama Hegde, Alexander Demkov, Philip Tobin, Dina Triyoso
-
Publication number: 20060094249Abstract: A method for forming a semiconductor structure including providing a semiconductor substrate, forming a metallic buffer layer over the semiconductor substrate, forming an amorphous semiconductor layer over the metallic buffer layer, and recrystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer. A semiconductor structure includes a semiconductor substrate, a buffer layer comprising at least one of silicide and germanide formed over the semiconductor substrate, and a crystalline semiconductor layer formed over the metallic buffer layer.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Inventors: Alexander Demkov, William Taylor
-
Publication number: 20060060928Abstract: A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.Type: ApplicationFiled: September 17, 2004Publication date: March 23, 2006Inventors: Sinan Goktepeli, Alexander Demkov, Marius Orlowski
-
Patent number: 6791125Abstract: A semiconductor device includes a continuous doped substrate with a surface, a sulfur-based dielectric material layer positioned on the surface of the continuous doped substrate, a dielectric material layer positioned on the sulfur-based dielectric material layer, and a gate contact region positioned on the sulfur-based dielectric material layer. The continuous doped substrate includes silicon (Si) and the sulfur-based dielectric material includes a transition metal sulfide such as strontium zirconium sulfur (SrZrS), barium zirconium sulfur (BaZrS), strontium hafnium sulfur (SrHfS), barium hafnium sulfur (BaHfS), or the like. Further, the gate contact region includes a layer of one of strontium titanium sulfur (SrTiS), barium titanium sulfur (BaTiS), or the like positioned adjacent to the dielectric material layer.Type: GrantFiled: September 30, 2002Date of Patent: September 14, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Alexander A. Demkov, Kurt W. Eisenbeiser
-
Publication number: 20040164315Abstract: Tunneling piezoelectric switch structures including high quality epitaxial layers of monocrystalline materials (26) grown overlying monocrystalline substrates (22) such as large silicon wafers are disclosed. The structures includes an accommodating buffer layer (24) spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer.Type: ApplicationFiled: February 25, 2003Publication date: August 26, 2004Applicant: MOTOROLA, INC.Inventor: Alexander A. Demkov
-
Publication number: 20040061188Abstract: A semiconductor device includes a continuous doped substrate with a surface, a sulfur-based dielectric material layer positioned on the surface of the continuous doped substrate, a dielectric material layer positioned on the sulfur-based dielectric material layer, and a gate contact region positioned on the sulfur-based dielectric material layer. The continuous doped substrate includes silicon (Si) and the sulfur-based dielectric material includes a transition metal sulfide such as strontium zirconium sulfur (SrZrS), barium zirconium sulfur (BaZrS), strontium hafnium sulfur (SrHfS), barium hafnium sulfur (BaHfS), or the like. Further, the gate contact region includes a layer of one of strontium titanium sulfur (SrTiS), barium titanium sulfur (BaTiS), or the like positioned adjacent to the dielectric material layer.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Alexander A. Demkov, Kurt W. Eisenbeiser