Abstract: A threaded interpreter (916) is suitable for executing a program comprising a series of program instructions stored in a memory (904).

Abstract: The problem of mis-match between a program counter (14) of a CPU (10) and a byte code counter (18) of an instruction path coprocessor (IPC) (16) is addressed by causing the IPC (16) to translate IPC branch instructions to the CPU branch instructions, in which the CPU branch instructions implicitly indicate whether a corresponding IPC branch instructions should be taken and in which the CPU branch instruction will cause the CPU (10) to set its own program counter (14) to a safe location in the IPC range to avoid overflow.

Abstract: An instruction path coprocessor (IPC) (16) observes the value of a CPU program counter (14) of a CPU (10) to detect whether the IPC (16) should be active. The IPC(1 6) uses the value of the CPU program counter also to determine how the IPC should update its own IPC program counter. When a function is called, an exception or interrupt is handled or a jump to a target specified in a register is executed, an address is prepared that, when loaded into the CPU program counter, will cause the IPC to update its IPC program counter as required for the return from function call, exception or interrupt or jump. The prepared address is loaded into the CPU (10) program counter.

Abstract: A score is computed of how many cache misses occur for the execution of each of a number of blocks. The score is used as a heuristic in a local search in which an original selection is iteratively replaced each time by a selection that differs from the original selection only by the movement of a single block and that has a lower number of cache misses for the sample of execution than the original selection. Thus a selection of locations for placing instructions of a program in main memory is found that minimizes the number of cache misses that occur for a sample of a typical execution of the program.

Abstract: A source program is executed on microcontroller core 114 of a processing unit 100. The core 114 is capable of native instructions from a predetermined set of micro-controller specific instructions. In a pre-processing step, for the program statements of the source program a program-specific virtual machine is defined with a corresponding set of virtual machine instructions, such that the expression of the program statements in the sequence of instructions requires less storage space compared to using only native instructions. For the program-specific virtual machine an associated conversion means 132 is defined for converting the program-specific virtual machine instructions into the native instructions of the core 114. The source program statements are expressed in a sequence of instructions comprising instructions of the defined virtual machine. The sequence of instructions is stored in an instruction memory 120. The conversion means 114 is represented in the processing unit 100.

Abstract: A method for structuring a multi-instruction computer program as containing a plurality of basic blocks, that each compose from internal instructions and external jumps organised in an internal directed acyclic graph. A guarding is executed on successor instructions that each collectively emanate from a respectively associated single predecessor instruction. A subset of joined instructions that converge onto a single join/target instruction are then unconditionally joined. This is accomplished by letting each respective instruction in the subset of joined instructions be executed under mutually non-related conditions, specifying all operations with respect to a jump instruction, specifying all operations that must have been executed previously, and linking various basic blocks comprising subsets of successor instructions in a directed acyclic graph which allows parallel execution of any further subset of instructions contained therein.

Abstract: Multiple format addressing is implemented in a microcontroller that has both ROM and RAM memory facility, processing facility, and bus facility for interconnecting the memory and processing facilities, through using a low address field for local addressing, and at least one facultative high address field for extended addressing. In particular, the high address field is provided in a first addressing format as a segment address, and in a second addressing format as containing a RAM/ROM selection bit. More in particular, the high address field can be provided in a third addressing format as containing a RAM/ROM selection bit and a segment address in respective mutually exclusive fields.

Abstract: A reproduction structure in a computer is based on a hierarchical structure of consistency relations between objects. As a function of one or more objects of a given hierarchical level, each relation specifies one or more incremental objects at a next-higher level. Variable incremental objects are situated at the lowest level. After a user interaction, modifying one or more variable incremental objects, the consistency is restored as follows. First a set of value inconsistencies is signaled for the incremental objects during a bottom-up signaling step. Subsequently, on the basis of each element of said set during a top-down updating step the value of the hierarchically higher object is updated on the basis of a change of value, if any, of associated, specifying variable incremental objects and/or incremental objects.

Abstract: A multi-media system for interactive presentation of user information has a physical interface for receiving removable and unitary mass storage elements for therein storing an interactive user program, and selectively accessing the mass storage element. The system accesses and processes the user program, for subsequent display of processing results, in response to particular user actuation on a level of elementary user functionality. In particular, the processing includes blockwise conversion to object code of machine-type generic multi-instruction blocks read from the storage to machine-type specific object-code blocks for subsequent selective accessing of the object code for processing.

Abstract: A reproduction structure in a computer is based on a hierarchical structure of consistency relations between objects. As a function of one or more objects of a given hierarchical level, each relation specifies one or more incremental objects at a next-higher level. Variable incremental objects are situated at the lowest level. After a user interaction, modifying one or more variable incremental objects, the consistency is restored as follows. First a set of value inconsistencies is signalled for the incremental objects during a bottom-up signalling step. Subsequently, on the basis of each element of said set during a top-down updating step the value of the hierarchically higher object is updated on the basis of a change of value, if any, of associated, specifying variable incremental objects and/or incremental objects.

Abstract: A method and apparatus is described for establishing a global binary assertion in a multiprocessor environment. The local objects have a three-value status variable: -active, disquiet-, -passive, quiet-, and -passive, disquiet- being the three values. First all local objects are made active. During execution, locally the assertion may hold, and thereupon a transition from active to -passive, quiet- is signalled to a global synchronizer process. Thereafter, cross-requests from a non-local object may reactivate a quiet object to the state -passive, disquiet-. The synchronizer process counts the transitions from active to -passive, quiet- and thus can detect when all objects are quiet. The local operations may represent a garbage collection system, wherein originally root items are colored grey and all other items white. In a marking phase, all grey items are successively accessed.