Patents by Inventor Alexander D. Breslow
Alexander D. Breslow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11762828Abstract: A method includes, for each key of a plurality of keys, identifying from a set of buckets a first bucket for the key based on a first hash function, and identifying from the set of buckets a second bucket for the key based on a second hash function. An entry for the key is stored in a bucket selected from one of the first bucket and the second bucket. The entry is inserted in a sequence of entries in a memory block. A position of the entry in the sequence of entries corresponds to the selected bucket. For each bucket in the set of buckets, an indication of a number of entries in the bucket is recorded.Type: GrantFiled: August 17, 2018Date of Patent: September 19, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Nuwan S. Jayasena
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Patent number: 11736119Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.Type: GrantFiled: April 18, 2022Date of Patent: August 22, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
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Patent number: 11586555Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.Type: GrantFiled: April 15, 2021Date of Patent: February 21, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, John Kalamatianos
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Publication number: 20220239315Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.Type: ApplicationFiled: April 18, 2022Publication date: July 28, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
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Patent number: 11309911Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.Type: GrantFiled: August 16, 2019Date of Patent: April 19, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
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Patent number: 11157174Abstract: A hybrid mechanism for operating on a data item in connection with an associative structure combines first-fit and K-choice. The hybrid mechanism leverages advantages of both approaches by choosing whether to insert, retrieve, delete, or modify a data item using either first-fit or K-choice. Based on the data item, a function of the data item, and/or other factors such as the load statistics of the associative structure, one of either first-fit or K-choice is used to improve operation on the associative structure across a variety of different load states of the associative structure.Type: GrantFiled: October 21, 2019Date of Patent: October 26, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Alexander D. Breslow, Nuwan Jayasena
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Publication number: 20210232505Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Inventors: Alexander D. Breslow, John Kalamatianos
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Publication number: 20210117100Abstract: A hybrid mechanism for operating on a data item in connection with an associative structure combines first-fit and K-choice. The hybrid mechanism leverages advantages of both approaches by choosing whether to insert, retrieve, delete, or modify a data item using either first-fit or K-choice. Based on the data item, a function of the data item, and/or other factors such as the load statistics of the associative structure, one of either first-fit or K-choice is used to improve operation on the associative structure across a variety of different load states of the associative structure.Type: ApplicationFiled: October 21, 2019Publication date: April 22, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Nuwan Jayasena
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Patent number: 10983915Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.Type: GrantFiled: August 19, 2019Date of Patent: April 20, 2021Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, John Kalamatianos
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Publication number: 20210056036Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.Type: ApplicationFiled: August 19, 2019Publication date: February 25, 2021Inventors: Alexander D. Breslow, John Kalamatianos
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Publication number: 20210050864Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.Type: ApplicationFiled: August 16, 2019Publication date: February 18, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
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Patent number: 10884948Abstract: A device includes an address translation table to, in each node of a set of nodes in the address translation table, store a key value and a hash function identifier, a hash engine coupled with the address translation table to, for each node in the set of nodes, calculate a hash result for the key value by executing a hash function identified by the hash function identifier, and a processing unit coupled with the hash engine to, in response to a request to translate a virtual memory address to a physical memory address, identify a physical memory region corresponding to the virtual memory address based on the calculated hash result for each node in the set of nodes.Type: GrantFiled: May 16, 2019Date of Patent: January 5, 2021Assignee: Advanced Micro Devices, Inc.Inventor: Alexander D. Breslow
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Publication number: 20200364150Abstract: A device includes an address translation table to, in each node of a set of nodes in the address translation table, store a key value and a hash function identifier, a hash engine coupled with the address translation table to, for each node in the set of nodes, calculate a hash result for the key value by executing a hash function identified by the hash function identifier, and a processing unit coupled with the hash engine to, in response to a request to translate a virtual memory address to a physical memory address, identify a physical memory region corresponding to the virtual memory address based on the calculated hash result for each node in the set of nodes.Type: ApplicationFiled: May 16, 2019Publication date: November 19, 2020Inventor: Alexander D. Breslow
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Publication number: 20200320016Abstract: A device includes an address translation buffer to, for each virtual page number of a plurality of virtual page numbers, store a mapping associated with the virtual page number. The mapping identifies a set of physical subpages allocated for the virtual page number, and the set of physical subpages includes at least a first physical subpage of a plurality of contiguous subpages in a physical memory region and excludes at least a second physical subpage of the plurality of contiguous subpages in the physical memory region. A memory management unit is coupled with the address translation buffer to, in response to receiving a requested virtual subpage number and a requested virtual page number of the plurality of virtual page numbers, determine, based on the mapping associated with the requested virtual page number, a physical subpage number identifying a physical subpage that is allocated for the requested virtual subpage number.Type: ApplicationFiled: April 8, 2019Publication date: October 8, 2020Inventor: Alexander D. Breslow
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Patent number: 10749545Abstract: A data storage system performs partial compression and decompression of a set of memory items. The memory items each include a data block and a tag with a prefix making up at least part of the tag. The memory items are ordered based on the prefixes. A code word is created containing compressed information representing values of the prefixes for the set of memory items. The code word and block data for each of the memory items are stored in a memory. The code word is decompressed to recover the prefixes.Type: GrantFiled: August 30, 2019Date of Patent: August 18, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
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Patent number: 10705972Abstract: Systems, apparatuses, and methods for determining preferred memory page management policies by software are disclosed. Software executing on one or more processing units generates a memory request. Software determines the preferred page management policy for the memory request based at least in part on the data access size and data access pattern of the memory request. Software conveys an indication of a preferred page management policy to a memory controller. Then, the memory controller accesses memory for the memory request using the preferred page management policy specified by software.Type: GrantFiled: September 13, 2016Date of Patent: July 7, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Amin Farmahini-Farahani, Alexander D. Breslow, Nuwan S. Jayasena
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Patent number: 10706101Abstract: Methods and mechanisms for managing data in a hash table are disclosed. A computing system includes a hash table configured to store data and hash management logic. In response to receiving a request to insert data into the hash table, the hash management logic is configured to generate a first hash value by applying a first hash function to the key of the key-value pair, and identify a first bucket within the hash table that corresponds to the first hash table. If the first bucket has a slot available, store the key-value pair in the slot. If the first bucket does not have a slot available, select a first slot of the first bucket for conversion to a remap entry, store the key-value pair in a second bucket, and store information associating the key-value pair with the second bucket in the remap entry.Type: GrantFiled: February 21, 2017Date of Patent: July 7, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Dong Ping Zhang, Nuwan S. Jayasena
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Publication number: 20200167327Abstract: A method of maintaining a probabilistic filter includes, in response to receiving a key K1 for adding to the probabilistic filter, generating a fingerprint F1 based on applying a fingerprint hash function HF to the key K1, identifying an initial bucket Bi1 by selecting between at least a first bucket B1 determined based on a first bucket hash function H1 of the key K1 and a second bucket B2 determined based on a second bucket hash function H2 of the key K1, and inserting the fingerprint F1 into the initial bucket Bi1; and resizing the probabilistic filter. Resizing the probabilistic filter includes incrementing a resize counter value, determining a bucket B? for the fingerprint F1 based on a value of the fingerprint F1 and the resize counter value, and inserting the fingerprint F1 into the bucket B? in the probabilistic filter.Type: ApplicationFiled: November 22, 2019Publication date: May 28, 2020Inventor: Alexander D. Breslow
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Patent number: 10409343Abstract: A cooling system is provided for a 3D integrated circuit (IC) to deliver fluid in x, y, and z dimensions to interior regions of the IC as a means to regulate heat. An IC includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system (MEMS)-based device that is disposed within the network of channels and that is configured to regulate a flow of fluid within the network of channels. Each sensor monitors a state of the IC. Each MEMS-based device receives control signals based on a state of the IC and regulates a flow of fluid within the network of channels based on control signals that area received on a real-time basis based on changes detected in a state of the IC.Type: GrantFiled: June 24, 2016Date of Patent: September 10, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Alexander D. Breslow, Dong Ping Zhang, Nuwan Jayasena
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Publication number: 20190266252Abstract: A method includes, for each key of a plurality of keys, identifying from a set of buckets a first bucket for the key based on a first hash function, and identifying from the set of buckets a second bucket for the key based on a second hash function. An entry for the key is stored in a bucket selected from one of the first bucket and the second bucket. The entry is inserted in a sequence of entries in a memory block. A position of the entry in the sequence of entries corresponds to the selected bucket. For each bucket in the set of buckets, an indication of a number of entries in the bucket is recorded.Type: ApplicationFiled: August 17, 2018Publication date: August 29, 2019Inventors: Alexander D. Breslow, Nuwan S. Jayasena