Abstract: The present invention relates generally to array oscillator circuits for use as phase delay generators. More particularly, the present invention relates to a novel array oscillator for providing a plurality of phases which have stable phase relationships. The present invention is particularly applicable to the generation of poly-phase clocks for receivers of very high speed interfaces which employ an over-sampling technique, or multiplexing, and for high speed logic. The array oscillator according to the invention comprises at least one ring oscillator having a plurality of at least two interconnected buffer stages including at least one, or any integer odd number of inverting stages and a series of non-inverting stages, wherein the buffer stages are formed of N-type MOSFET transistors.

Abstract: A reference voltage generator employs a ring oscillator having a plurality of logic stages and a phase/frequency detector, for generating a first feedback signal on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator; and to generate a second feedback signal on the basis of a voltage swing of the oscillator circuit; both feedback signals to be applied to said plurality of logic stages of the ring oscillator; whereby a constant delay is created through each logic stage of the logic device. In another aspects of the invention, a method of generating a reference voltage for a logic device by using the reference voltage generator as above and a logic device with a controlled propagation delay of each of the logic stages are provided.

Abstract: An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.