Patents by Inventor Alexander Eglit
Alexander Eglit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080056421Abstract: An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount of look-behind and look-ahead information in order to improve upon simple symbol-by-symbol detection. The over-sampled information is used to further improve detection performance.Type: ApplicationFiled: October 31, 2007Publication date: March 6, 2008Applicant: Genesis Microchip Inc.Inventor: Alexander Eglit
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Publication number: 20070071153Abstract: An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount of look-behind and look-ahead information in order to improve upon simple symbol-by-symbol detection. The over-sampled information is used to further improve detection performance.Type: ApplicationFiled: September 28, 2005Publication date: March 29, 2007Inventor: Alexander Eglit
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Publication number: 20060133540Abstract: An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases and then picks a sample sequence that allows for the most reliable detection. For the different sampling phases, the detector inspects some amount of look-behind and look-ahead information in order to improve upon simple symbol-by-symbol detection. The over-sampled information is used to further improve detection performance.Type: ApplicationFiled: February 28, 2005Publication date: June 22, 2006Inventor: Alexander Eglit
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Patent number: 6023266Abstract: Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.Type: GrantFiled: December 3, 1996Date of Patent: February 8, 2000Assignee: Cirrus Logic, Inc.Inventors: Alexander Eglit, Rakesh Kumar Bindlish, Vlad Bril
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Patent number: 5682170Abstract: A method and apparatus for horizontally and vertically positioning a video graphics adapter (VGA) display image on the screen of a flat panel display (FPD) is provided with a first counter for setting a horizontal FPD disable period associated with the FPD. A second counter sets the horizontal FPD enable period of the FPD. This horizontal FPD enable period is greater than a composite horizontal pixel time of a VGA image to be displayed. A first circuit controls the start time of a subsequent horizontal FPD enable period. This start time is based on the horizontal FPD disable period. A second circuit controls the end time of the subsequent horizontal FPD enable period. This end time is based on the horizontal FPD enable period. The VGA display image is begun based on the start time of the subsequent horizontal FPD enable period to locate the VGA display image at a desired horizontal position of the FPD screen. The vertical positioning of the image is performed by similar counters and circuits.Type: GrantFiled: July 31, 1995Date of Patent: October 28, 1997Assignee: Cirrus Logic, Inc.Inventors: Sridhar Kotha, Alexander Eglit, Robin Han
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Patent number: 5642139Abstract: Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.Type: GrantFiled: April 29, 1994Date of Patent: June 24, 1997Assignee: Cirrus Logic, Inc.Inventors: Alexander Eglit, Rakesh Kumar Bindlish, Vlad Bril
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Patent number: 5611041Abstract: A memory controller, particularly for use in a video controller, is provided which reduces the effect of page misses during memory access. A video port FIFO is provided for buffering data from a video port to a display memory. A CRT FIFO is provided for buffering data from a display memory to a display. If, during a video port FIFO cycle, a page miss is encountered, the video port FIFO cycle is terminated and processing passes to a CRT FIFO CYCLE. If a page miss is encountered during a CRT FIFO cycle, the subsequent video port FIFO cycle will shortened by a number of memory cycles to compensate for the additional memory cycles required by the page miss. Additional data accumulated in the video port FIFO may be transferred to the display memory during a retrace interval. In this manner, memory bandwidth is optimized by removing a non-aligned page miss as the worst case of memory bandwidth utilization.Type: GrantFiled: December 19, 1994Date of Patent: March 11, 1997Assignee: Cirrus Logic, Inc.Inventors: Vlad Bril, Alexander Eglit, Sagar W. Kenkare
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Patent number: 5608864Abstract: A computer video controller, particularly a VGA or SVGA video controller for use with graphical user interface (GUI) software such as WINDOWS.TM. or OS/2.TM. is provided with two video data pipelines for simultaneously displaying full motion video within a window in a video display. A first data pipeline displays background video at a first pixel depth. A second data pipeline is provided to display a motion video window at a second, usually higher, pixel depth. The location of the motion video window is measured horizontally in number of memory fetch cycles needed to retrieve the horizontal scan line of pixel data abutting the motion video window. The width of the motion video window is measured in the number of memory fetches required to retrieve one scan line of the motion video window.Type: GrantFiled: April 29, 1994Date of Patent: March 4, 1997Assignee: Cirrus Logic, Inc.Inventors: Rakesh K. Bindlish, Vlad Bril, Alexander Eglit
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Patent number: 5521614Abstract: A method and apparatus for expanding a video graphics adapter (VGA) text character to fully fill the screen of a flat panel display. The present invention stores binary information representing a horizontal row of character text. A prescribed bit in the binary information may be set to determine whether to duplicate pixels associated with the binary information in either a horizontal or vertical direction. A circuit is provided to ensure that foreground and background characteristics of the graphics character text being expanded are consistent with the sent prescribed bit in the binary information.Type: GrantFiled: April 29, 1994Date of Patent: May 28, 1996Assignee: Cirrus Logic, Inc.Inventors: Sridhar Kotha, Alexander Eglit, Robin Han