Patents by Inventor Alexander Gorer

Alexander Gorer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7658790
    Abstract: An electroless solution for deposition of a cobalt-based alloy on a substrate is provided. The electroless solution may be formed by mixing first and second solutions, with the first and second solutions being prepared from concentrated precursors. In one embodiment, the first solution contains a cobalt (Co) ion source and a complexing and deposition selectivity agent. In one embodiment, the cobalt concentration in the first solution is at least 90 millimoles per liter. The second solution contains a reducing agent. In one embodiment, the reducing agent is dimethylamineborane (DMAB) having a concentration of at least 10 grams per liter. In other embodiments, the first solution also contains a tungsten (W) ion source, and either the first or second solution also contains a phosphorous (P) ion source.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: February 9, 2010
    Assignee: Intermolecular, Inc.
    Inventors: Alexander Gorer, Tony Chiang, Chi-I Lang
  • Patent number: 7635533
    Abstract: An improved metal alloy composition for a fuel cell catalyst containing platinum, manganese, and cobalt.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: December 22, 2009
    Assignees: Symyx Solutions, Inc., Honda Giken Kogyo Kabushike Kaisha
    Inventors: Qun Fan, Peter Strasser, Alexander Gorer, Martin Devenney, Konstantinos Chondroudis, Daniel M. Giaquinta, Ting He, Hiroyuki Oyanagi, Kenta Urata, Kazuhiko Iwasaki, Hiroichi Fukuda
  • Publication number: 20090278110
    Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.
    Type: Application
    Filed: May 8, 2009
    Publication date: November 12, 2009
    Inventors: Alexander Gorer, Prashant Phatak, Tony Chiang, Igor Ivanov
  • Patent number: 7608560
    Abstract: A fuel cell catalyst comprising platinum, titanium and tungsten. In one or more embodiments, the concentration of platinum is less than 60 atomic percent, and/or the concentration of titanium is at least 20 atomic percent, and/or the concentration of tungsten is at least 25 atomic percent.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: October 27, 2009
    Assignees: Symyx Technologies, Inc., Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Qun Fan, Peter Strasser, Alexander Gorer, Martin Devenney, Ting He, Hiroyuki Oyanagi, Daniel M. Giaquinta, Kenta Urata, Hiroichi Fukuda, Konstantinos Chondroudis, Keith James Cendak
  • Publication number: 20090227049
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: May 4, 2009
    Publication date: September 10, 2009
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Patent number: 7544574
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: June 9, 2009
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Patent number: 7501208
    Abstract: An active manganese dioxide electrode material that exhibits improved electrochemical performances compared with conventional manganese dioxide materials includes at least one dopant. The doped manganese dioxide electrode materials may be produced by a wet chemical method (CMD) or may be prepared electrolytically (EMD) using a solution containing manganese sulfate, sulfuric acid, and a dopant, wherein the dopant is present in an amount of at least about 25 ppm.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: March 10, 2009
    Assignee: Eveready Battery Company, Inc.
    Inventors: Frank H. Feddrix, Scott W. Donne, Martin Devenney, Alexander Gorer
  • Patent number: 7485390
    Abstract: The present invention is directed to a method for forming combinatorial libraries comprising arrays of materials prepared by depositing a metal species on a support for use as catalysts, such as electrocatalysts. The invention is also directed to combinatorial libraries comprising an array of such metal-containing supported catalysts. These catalyst-containing libraries are particularly well-suited for use in conducting combinatorial research investigations, in particular with respect to electrocatalysts for fuel cells.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: February 3, 2009
    Inventors: Martin Devenney, Konstantinos Chondroudis, Alexander Gorer
  • Patent number: 7479343
    Abstract: A fuel cell electrocatalyst that contains platinum, indium, and at least one of tungsten, iron, and manganese.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: January 20, 2009
    Assignees: Symyx Technologies, Inc., Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Martin Devenney, Alexander Gorer, Peter Strasser, Ting He, Hiroyuki Oyanagi, Daniel M. Giaquinta, Qun Fan, Konstantinos Chondroudis
  • Patent number: 7422994
    Abstract: A composition for use as a catalyst in, for example, a fuel cell, the composition comprising platinum, copper and tungsten, or an oxide, carbide and/or salt of one or more of platinum, copper and tungsten, wherein the sum of the concentrations of platinum, copper and tungsten, or an oxide, carbide and/or salt thereof, is greater than 90 atomic percent.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: September 9, 2008
    Assignees: Symyx Technologies, Inc., Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Konstantinos Chondroudis, Alexander Gorer, Peter Strasser, Martin Devenney, Qun Fan, Daniel M. Giaquinta, Keith James Cendak, Hiroyuki Oyanagi, Kenta Urata
  • Publication number: 20080166623
    Abstract: The present invention is directed to a composition for use as a catalyst in, for example, a fuel cell, the composition comprising platinum, nickel, and iron, wherein (i) the concentration of platinum is greater than 50 atomic percent, the concentration of nickel is less than 15 atomic percent and/or the concentration of iron is greater than 30 atomic percent, or (ii) the concentration of platinum is greater than 70 atomic percent and less than about 90 atomic percent. The present invention is further directed to a process for preparing such a catalyst composition from a catalyst precursor composition comprising platinum, nickel, and iron, wherein the concentration of platinum therein is less than 50 atomic percent.
    Type: Application
    Filed: September 3, 2004
    Publication date: July 10, 2008
    Applicants: Symyx Technologies, Inc., Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Keith James Cendak, Jennifer N. Cendak, Peter Strasser, Alexander Gorer, Martin Devenney, Ting He, Hiroyuki Oyanagi, Qun Fan, Konstantinos Chondroudis, Daniel M. Giaquinta, Kenta Urata, Kazuhiko Iwasaki, Hiroichi Fukuda
  • Publication number: 20080133161
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: February 11, 2008
    Publication date: June 5, 2008
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Publication number: 20080132089
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: February 8, 2008
    Publication date: June 5, 2008
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Publication number: 20080128696
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: February 12, 2008
    Publication date: June 5, 2008
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Patent number: 7361257
    Abstract: Devices and methods for evaluating an electrochemical reaction are disclosed. A device includes an electrochemical cell having a cavity for containing a liquidus electrolyte, a first working electrode having at least one electrolytic surface at least partially within the cavity, and a second counter electrode having at least one electrolytic surface at least partially within the cavity. The first working electrode includes a body and an insert supported by the body. The electrolytic surface of the working electrode is formed on or integral with the insert. The insert and body are each formed from a high-temperature material which allows for preparation or processing of the electrolytic surface at a temperature of at least 300° C. The device further includes a drive system detachably coupled to the first working electrode or a portion thereof for effecting relative motion between the electrolytic surface of the working electrode and a bulk portion of the liquidus electrolyte.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: April 22, 2008
    Assignee: Symyx Technologies, Inc.
    Inventors: Youqi Wang, Martin Devenney, Alexander Gorer
  • Publication number: 20080044719
    Abstract: A composition for use as a catalyst in, for example, a fuel cell, the composition comprising platinum, copper and titanium, or an oxide, carbide and/or salt of one or more of platinum, copper and titanium, wherein the sum of the concentrations of platinum, copper and titanium, including an oxide, carbide and/or salt thereof, is greater than about 90 atomic percent.
    Type: Application
    Filed: January 27, 2006
    Publication date: February 21, 2008
    Applicants: Symyx Technologies, Inc., Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Alexander Gorer, Peter Strasser, Qun Fan, Konstantinos Chondroudis, Daniel Giaquinta, Keith Cendak, Hiroyuki Oyanagi, Kenta Urata
  • Publication number: 20070202610
    Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 30, 2007
    Inventors: Tony Chiang, David Lazovsky, Kurt Weiner, Gustavo Pinto, Thomas Boussie, Alexander Gorer
  • Publication number: 20070202614
    Abstract: A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 30, 2007
    Inventors: Tony Chiang, David Lazovsky, Kurt Weiner, Gustavo Pinto, Thomas Boussie, Alexander Gorer
  • Publication number: 20070089857
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: February 10, 2006
    Publication date: April 26, 2007
    Inventors: Tony Chiang, David Lazovsky, Thomas Boussie, Thomas McWaid, Alexander Gorer
  • Publication number: 20070082487
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: February 10, 2006
    Publication date: April 12, 2007
    Inventors: Tony Chiang, David Lazovsky, Thomas Boussie, Alexander Gorer