Patents by Inventor Alexander H. Nickel

Alexander H. Nickel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170675
    Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
    Type: Grant
    Filed: July 29, 2017
    Date of Patent: January 1, 2019
    Assignee: LUMILEDS LLC
    Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
  • Publication number: 20180323353
    Abstract: A light-emitting device is described herein. The device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The device also includes a metal layer with openings formed therein and filled with an insulating material. The openings separate the metal layer into a first portion that is electrically isolated from a second portion. The first portion is coupled to the n-type region and the second portion coupled to the p-type region. The device also includes conductive stacks. A first surface of each of the conductive stacks contacts a surface of the metal layer opposite the semiconductor structure. A respective gap is positioned between each of the conductive stacks. A body is in direct contact with a second surface of each of the conductive stacks that is opposite the first surface.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 8, 2018
    Applicant: Lumileds LLC
    Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel
  • Patent number: 10020431
    Abstract: A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: July 10, 2018
    Assignee: Lumileds LLC
    Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel
  • Patent number: 9935069
    Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: April 3, 2018
    Assignee: LUMILEDS LLC
    Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel, Mooi Guan Ng, Salman Akram
  • Publication number: 20170373235
    Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
    Type: Application
    Filed: July 29, 2017
    Publication date: December 28, 2017
    Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
  • Patent number: 9722161
    Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 1, 2017
    Assignee: Koninklijke Philips N.V.
    Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
  • Patent number: 9608016
    Abstract: A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: March 28, 2017
    Assignee: Koninklijke Philips N.V.
    Inventors: Jipu Lei, Alexander H. Nickel, Stefano Schiaffino, Grigoriy Basin
  • Patent number: 9484513
    Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: November 1, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
  • Patent number: 9425325
    Abstract: The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: August 23, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Jeong-Uk Huh
  • Publication number: 20160233400
    Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
  • Patent number: 9406857
    Abstract: Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: August 2, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel, Mooi Guan Ng, Grigoriy Basin, Salman Akram
  • Publication number: 20160181216
    Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.
    Type: Application
    Filed: June 5, 2014
    Publication date: June 23, 2016
    Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel, Mooi Guan Ng, Salman Akram
  • Publication number: 20160126436
    Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
    Type: Application
    Filed: December 21, 2015
    Publication date: May 5, 2016
    Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
  • Patent number: 9324927
    Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: April 26, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
  • Patent number: 9219209
    Abstract: A light emitting diode (LED) structure (10) has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer (34) is formed in the gap followed by filling the gap with a metal (42). The metal is patterned to form stud bumps (40, 42, 44) that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: December 22, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiafino, Daniel Alexander Steigerwald
  • Publication number: 20150144971
    Abstract: Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.
    Type: Application
    Filed: June 4, 2013
    Publication date: May 28, 2015
    Inventors: Jipu Lei, Stefano Schiaffino, ALexander H. Nickel, Mooi Guan Ng, Grigoriy Basin, Salman Akram
  • Publication number: 20150140711
    Abstract: A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.
    Type: Application
    Filed: May 8, 2013
    Publication date: May 21, 2015
    Inventors: Jipu Lei, Alexander H. Nickel, Stefano Schiaffino, Grigoriy Basin
  • Publication number: 20150076538
    Abstract: A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.
    Type: Application
    Filed: March 22, 2013
    Publication date: March 19, 2015
    Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel
  • Publication number: 20140339597
    Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.
    Type: Application
    Filed: December 4, 2012
    Publication date: November 20, 2014
    Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
  • Patent number: 8735960
    Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: May 27, 2014
    Assignee: Spansion LLC
    Inventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Sung Jin Kim, Simon Chan, Ning Cheng