Patents by Inventor Alexander H. Nickel
Alexander H. Nickel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10170675Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.Type: GrantFiled: July 29, 2017Date of Patent: January 1, 2019Assignee: LUMILEDS LLCInventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
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Publication number: 20180323353Abstract: A light-emitting device is described herein. The device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The device also includes a metal layer with openings formed therein and filled with an insulating material. The openings separate the metal layer into a first portion that is electrically isolated from a second portion. The first portion is coupled to the n-type region and the second portion coupled to the p-type region. The device also includes conductive stacks. A first surface of each of the conductive stacks contacts a surface of the metal layer opposite the semiconductor structure. A respective gap is positioned between each of the conductive stacks. A body is in direct contact with a second surface of each of the conductive stacks that is opposite the first surface.Type: ApplicationFiled: July 9, 2018Publication date: November 8, 2018Applicant: Lumileds LLCInventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel
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Patent number: 10020431Abstract: A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.Type: GrantFiled: March 22, 2013Date of Patent: July 10, 2018Assignee: Lumileds LLCInventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel
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Patent number: 9935069Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.Type: GrantFiled: June 5, 2014Date of Patent: April 3, 2018Assignee: LUMILEDS LLCInventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel, Mooi Guan Ng, Salman Akram
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Publication number: 20170373235Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.Type: ApplicationFiled: July 29, 2017Publication date: December 28, 2017Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
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Patent number: 9722161Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.Type: GrantFiled: December 21, 2015Date of Patent: August 1, 2017Assignee: Koninklijke Philips N.V.Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
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Patent number: 9608016Abstract: A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.Type: GrantFiled: May 8, 2013Date of Patent: March 28, 2017Assignee: Koninklijke Philips N.V.Inventors: Jipu Lei, Alexander H. Nickel, Stefano Schiaffino, Grigoriy Basin
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Patent number: 9484513Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.Type: GrantFiled: April 18, 2016Date of Patent: November 1, 2016Assignee: Koninklijke Philips N.V.Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
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Patent number: 9425325Abstract: The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.Type: GrantFiled: January 13, 2014Date of Patent: August 23, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Jeong-Uk Huh
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Publication number: 20160233400Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.Type: ApplicationFiled: April 18, 2016Publication date: August 11, 2016Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
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Patent number: 9406857Abstract: Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.Type: GrantFiled: June 4, 2013Date of Patent: August 2, 2016Assignee: Koninklijke Philips N.V.Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel, Mooi Guan Ng, Grigoriy Basin, Salman Akram
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Publication number: 20160181216Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.Type: ApplicationFiled: June 5, 2014Publication date: June 23, 2016Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel, Mooi Guan Ng, Salman Akram
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Publication number: 20160126436Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.Type: ApplicationFiled: December 21, 2015Publication date: May 5, 2016Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiaffino, Daniel Alexander Steigerwald
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Patent number: 9324927Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.Type: GrantFiled: December 4, 2012Date of Patent: April 26, 2016Assignee: Koninklijke Philips N.V.Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
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Patent number: 9219209Abstract: A light emitting diode (LED) structure (10) has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer (34) is formed in the gap followed by filling the gap with a metal (42). The metal is patterned to form stud bumps (40, 42, 44) that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.Type: GrantFiled: April 25, 2012Date of Patent: December 22, 2015Assignee: Koninklijke Philips N.V.Inventors: Jipu Lei, Yajun Wei, Alexander H. Nickel, Stefano Schiafino, Daniel Alexander Steigerwald
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Publication number: 20150144971Abstract: Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.Type: ApplicationFiled: June 4, 2013Publication date: May 28, 2015Inventors: Jipu Lei, Stefano Schiaffino, ALexander H. Nickel, Mooi Guan Ng, Grigoriy Basin, Salman Akram
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Publication number: 20150140711Abstract: A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.Type: ApplicationFiled: May 8, 2013Publication date: May 21, 2015Inventors: Jipu Lei, Alexander H. Nickel, Stefano Schiaffino, Grigoriy Basin
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Publication number: 20150076538Abstract: A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.Type: ApplicationFiled: March 22, 2013Publication date: March 19, 2015Inventors: Jipu Lei, Stefano Schiaffino, Alexander H. Nickel
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Publication number: 20140339597Abstract: A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.Type: ApplicationFiled: December 4, 2012Publication date: November 20, 2014Inventors: Stefano Schiaffino, Alexander H. Nickel, Jipu Lei
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Patent number: 8735960Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.Type: GrantFiled: November 17, 2008Date of Patent: May 27, 2014Assignee: Spansion LLCInventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Sung Jin Kim, Simon Chan, Ning Cheng