Abstract: A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t0) of the operation of the circuit design, representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model, describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations, storing the plurality of linear equations in a matrix Y0 for time t0, resolving the matrix Y0 to determine a DC operating point, updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t1=t+h where h is a time step value equal to the current time t and a next simulated operation time, storing the updated plurality of linear equations in a matrix Y1 for ti

Abstract: This invention provides techniques and tools for reducing circuit simulation time when an electronic circuit with multiple input vectors is simulated. Instead of running the simulation for each input vector one at a time, the circuit-simulation application runs the simulation of the circuit for all input vectors simultaneously. Efficiencies in the simulation are obtained during each iteration of a transient analysis by grouping circuit instances with different input vectors based on a predetermined criteria, and producing a combined solution for circuit instances within each group.

Abstract: A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t0) of the operation of the circuit design, representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model, describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations, storing the plurality of linear equations in a matrix Y0 for time t0, resolving the matrix Y0 to determine a DC operating point, updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t1=t+h where h is a time step value equal to the current time t and a next simulated operation time, storing the updated plurality of linear equations in a matrix Y1 for ti

Abstract: Prediction of a clock skew for an incomplete integrated circuit design, includes (a) selecting a first metal layer having at least one clock design figure, (b) placing, for a minimum clock skew prediction, clock source locations on the clock design figure in accordance with a first predetermined minimum distance between adjacent clock source locations, (c) placing, for a maximum clock skew prediction, a clock source location on a largest clock design figure in the first layer, such that the clock source location has a largest distance from a via to a lower layer, and (d) placing, for an intermediate clock skew prediction, clock source locations on intersections between the clock design figure and a virtual clock grid created for the first metal layer, the virtual clock grid having a predetermined offset from a design boundary and a predetermined pitch between grid lines.

Abstract: A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC design area. The method includes (a) dividing the IC design area into a second plurality of sub-areas, (b) assigning an area property to each of the data objects, the area property indicating the sub-areas on which at least part of the corresponding design figure is to be located, (c) selecting a first data object, and (d) conducting an operation involving the first data object and a second data object involving selecting the second data object from a subset of data objects having an area property indicating a sub-area indicated by an area property of the first data object, and performing the operation on the first data object and the second data object.

Abstract: A method for allocating decoupling capacitor cells in an integrated circuit (IC) design, includes (a) obtaining geometrical information of rectangular areas in the IC design, each of the rectangular areas not intersecting any design figure in selected metal layers of the IC design in a design area, (b) determining possible locations for rows of decoupling capacitor cell arrays to be placed in the rectangular areas, a row including a set of cell arrays to be placed across the rectangular areas in a direction of a first coordinate axis of the design area, (c) determining for each possible location a number of decoupling capacitor cells included in the row, and (d) selecting row locations satisfying a certain design rule from among the possible locations in a descending order of the number of the decoupling capacitor cells.

Abstract: A method for allocating decoupling capacitor cells in an integrated circuit (IC) design, includes (a) obtaining geometrical information of rectangular areas in the IC design, each of the rectangular areas not intersecting any design figure in selected metal layers of the IC design in a design area, (b) determining possible locations for rows of decoupling capacitor cell arrays to be placed in the rectangular areas, a row including a set of cell arrays to be placed across the rectangular areas in a direction of a first coordinate axis of the design area, (c) determining for each possible location a number of decoupling capacitor cells included in the row, and (d) selecting row locations satisfying a certain design rule from among the possible locations in a descending order of the number of the decoupling capacitor cells.

Abstract: A method and system for providing a realizable reduced-order model for a circuit. The method includes calculating a value for each component of said realizable reduced-order model. The calculating is based upon properties of a signal provided to the circuit and a voltage range associated with the circuit. If at least one of the values is not positive, the voltage range is modified and the calculating step is repeated until each of the values is positive.

Abstract: A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC design area. The method includes (a) dividing the IC design area into a second plurality of sub-areas, (b) assigning an area property to each of the data objects, the area property indicating the sub-areas on which at least part of the corresponding design figure is to be located, (c) selecting a first data object, and (d) conducting an operation involving the first data object and a second data object involving selecting the second data object from a subset of data objects having an area property indicating a sub-area indicated by an area property of the first data object, and performing the operation on the first data object and the second data object.

Abstract: The present invention, which may be implemented on a general-purpose digital computer, in certain embodiments includes novel methods and apparatus to provide accurate prediction for skew or delay analysis in complex multi-stage signal paths with mutual couplings between the stages. In some embodiments, single or multiple processors are utilized to implement the present invention.