Abstract: A proportional counting circuit generates count values for use in variably adjusting gain and exposure time of an image sensor array. The count values are adjusted in proportion to the current count value. This technique allows for fast and accurate adjustment of gain and exposure time without sacrificing the visual performance defined by the contrast difference. At least one break-in signal disables counting in some lower bits when a particular higher bit is asserted and allows the count values to be adjusted by a different increment when the count value reaches a predetermined value by asserting the particular higher bit. Break-out signals are used in less significant bits to disable counting in all lower bits than the bit being disabled by the break-in signal from the more significant bit.

Abstract: An image sensing device, such as a CMOS Active Pixel Sensor (APS) device, includes an array of pixels. Each pixel includes a reset transistor connected between a photodetector and a supply voltage. In a readout operation, a signal integrated onto the photodetector is sampled onto a holding capacitor. The photodetector is then reset in a reference reset operation during which the photodetector is clamped to the supply voltage. A reset signal is sampled from the pixel while the photodetector is clamped to the supply voltage. Reset, or kTC, noise in the reset signal may be filtered by a source-follower transistor in the pixel.

Abstract: Automatic exposure adjusting device considers the image on a pixel-by-pixel basis. Each pixel is characterized according to its most significant bits. After the pixels are characterized, the number of pixels in any particular group is counted. That counting is compared with thresholds which set whether the image is over exposed, under exposed, and can optionally also determine if the image is seriously over exposed or seriously under exposed. Adjustment of the exposure is carried out to bring the image to a more desired state.

Abstract: A CMOS imager includes an array of active pixel sensors, wherein each pixel is associated with a respective column in the array. The imager also includes multiple circuits for reading out values of pixels from the active sensor array. Each readout circuit can be associated with a respective pair of columns in the array and can include first and second sample-and-hold circuits. The first and second sample-and-hold circuits are associated, respectively, with first and second columns of pixels in the array. Each readout circuit also includes an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit. The readout circuit also has an analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique.

Abstract: A signal chain for an image sensor is disclosed. The signal chain includes photo sensing elements, pixel readout circuits, and an amplifier. Each pixel readout circuit receives a charge-induced signal and a reset signal from one of the photo sensing elements. The readout circuit computes a difference signal between the charge-induced signal and said reset signal. The difference signal is measured with respect to a reference signal. The amplifier is coupled to the pixel readout circuits, and configured to supply the reference signal during computation of the difference signal. Further, the amplifier amplifies the difference signal when the computation is done.

Abstract: An A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply is disclosed. The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor.

Abstract: A CMOS Active Pixel Sensor (APS) uses a pinned photodiode as a photoreceptor and negative-channel metal-oxide semiconductor (NMOS) transistors in the sample and hold and reset circuits of the frame shutter. The pinned photodiode increases the quantum efficiency and reduces the dark current. The NMOS transistors in the frame shutter increase the fill factor and reduce the pixel pitch.

Abstract: A shutter system for a pixel array is disclosed. The system includes a read shift register, first and second reset shift registers, and a plurality of logic gates. The read shift register is configured to sequentially count rows of the pixel array from top to bottom, such that the read shift register generates a read pointer. The first reset shift register is configured to sequentially reset rows of the pixel array from top to bottom. The first reset shift register provides a first reset pointer for allowing reset of pixels in a row indicated by the first reset pointer. The first reset pointer allows reset of pixels prior to reading of the pixels in a row indicated by the read pointer. The time difference between the first reset pointer and the read pointer indicates an exposure time.

Abstract: An A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply is disclosed. The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor.

Abstract: An A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply is disclosed. The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor.

Abstract: An apparatus has a pixel that includes (i) a buffer transistor having an input, (ii) first and second capacitive storage elements each of which selectively can be coupled to the input of the buffer transistor, and (iii) a photosensitive element having an output which selectively can be coupled to the input of the buffer transistor. A readout circuit selectively can be coupled to an output of the buffer transistor. A first signal level, sensed by the photosensitive element, can be stored by the first capacitive storage element, and a second signal level, sensed by the photosensitive element, can be stored by the second capacitive storage element. The first and second signal levels can be read out from the pixel.

Abstract: An image sensing device, such as a CMOS Active Pixel Sensor (APS) device, includes an array of pixels. Each pixel includes a reset transistor connected between a photodetector and a supply voltage. In a readout operation, a signal integrated onto the photodetector is sampled onto a holding capacitor. The photodetector is then reset in a reference reset operation during which the photodetector is clamped to the supply voltage. A reset signal is sampled from the pixel while the photodetector is clamped to the supply voltage. Reset, or kTC, noise in the reset signal may be filtered by a source-follower transistor in the pixel.

Abstract: An A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply is disclosed. The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor.

Abstract: An A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply is disclosed. The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor.

Abstract: Wide dynamic range operation is used to write a signal in a freeze-frame pixel into the memory twice, first after short integration and then after long integration. The wide dynamic range operation allows the intra-scene dynamic range of images to be extended by combining the image taken with a short exposure time with the image taken with a long exposure time. A freeze-frame pixel is based on voltage sharing between the photodetector PD and the analog memory. Thus, with wide dynamic range operation, the resulting voltage in the memory may be a linear superposition of the two signals representing a bright and a dark image after two operations of sampling.

Abstract: A CMOS Active Pixel Sensor (APS) uses a pinned photodiode as a photoreceptor and negative-channel metal-oxide semiconductor (NMOS) transistors in the sample and hold and reset circuits of the frame shutter. The pinned photodiode increases the quantum efficiency and reduces the dark current. The NMOS transistors in the frame shutter increase the fill factor and reduce the pixel pitch.

Abstract: Smarts are added to a CMOS active pixel color linear image sensor operable in any of parallel-packed, pixel-packed, and line-packed readout mode, to provide the added feature of variable imaging resolution operability. By combining decoder block functionality with shift selection logic to provide column selection adaptable for lowering the resolution of an imaging process, higher speed imaging is possible. Furthermore, the added functionality is implemented in a manner which does not unduly impact chip size. More importantly, the added functionality is compatible with, and in fact complements the specific architecture of an active pixel color linear sensor with variable readout mode functionality incorporated therein.

Abstract: A circuit for use in comparing input voltages includes switching elements initially configured in a reset mode to minimize charge or current conduction before entering a comparison mode. A strobe signal reconfigures the switching elements to transition from the reset mode to the comparison mode. Finally, a determination is made as to which of the input voltages is larger or smaller.

Abstract: A low voltage comparator for amplifying a voltage difference between a pair of differential inputs. A boost capacitor charges to a boost voltage in excess of the low supply voltage, a differential pair of MOSFET transistors, each said transistor including a gate, a source, a drain, and a body terminal. The comparator also includes a latch mechanism built from a cross-coupled pair of MOSFET transistors for latching the compared result. A well capacitor is used to charge the body terminal of the differential pair where the boost capacitor and the well capacitor boost the common source voltage and reduce the threshold voltage of the differential pair to allow the supply voltage to be at relatively low level.

Abstract: The present disclosure describes a low-voltage switched-capacitor amplifier circuit that operates with supply voltage as low as one volt. The switched-capacitor amplifier circuit includes a voltage-amplifying transistor configured in a switched-capacitor network by an input capacitor and a feedback capacitor. The gate terminal of the voltage-amplifying transistor is connected to the supply voltage through a first switch that turns on during stage 1 of the reset phase. During stage 2, the first switch opens and a second switch is closed. The second switch is in series with a second transistor. The second transistor maintains certain voltage difference between the input and the output and keeps the output voltage from pulling the input voltage down to ground.