Patents by Inventor Alexander IVANIUK
Alexander IVANIUK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11818248Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder.Type: GrantFiled: June 2, 2022Date of Patent: November 14, 2023Assignee: SK hynix Inc.Inventors: Siarhei Zalivaka, Alexander Ivaniuk
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Publication number: 20230266944Abstract: A circuit and associated method for providing a true random and unclonable output from the circuit. In the circuit and method, an enable signal is received at a first port of a latch, and a data input signal is received at a second port of the latch. Via an inverter coupled to the latch circuit, an inversion signal of output data from the latch is generated. The inversion of the signal is fed to the second port, and the latch circuit and the inverter are operated to provide the true random and unclonable output.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventors: Alexander IVANIUK, Siarhei ZALIVAKA
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Patent number: 11650914Abstract: A system which identifies a memory device using a physical unclonable function. The system performs raw read operations on every page of a block; sorts the pages into low and high groups using an average number of ones based on the raw read operations; generates unordered page pairs by sequentially selecting a first page from the low group and a second page from the high group; generates ordered page pairs by selectively converting an order of pages in each pair of the unordered page pairs; and generates a sequence for identifying the selected block based on comparing the average number of ones for pages in each ordered page pair.Type: GrantFiled: August 5, 2021Date of Patent: May 16, 2023Assignee: SK hynix Inc.Inventors: Siarhei Zalivaka, Alexander Ivaniuk
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Patent number: 11650795Abstract: A multi-level memory cell NAND structure of a memory device is utilized to extract uniqueness from the memory device. Certain unreliable characteristics of a NAND-based storage are used to generate a true random number sequence. A method for generating such sequence is based on a physically unclonable function (PUF) which is implemented by extracting unique characteristics of a NAND-based memory device using existing firmware procedures.Type: GrantFiled: August 23, 2019Date of Patent: May 16, 2023Assignee: SK hynix Inc.Inventors: Siarhei Zalivaka, Alexander Ivaniuk
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Patent number: 11635916Abstract: Compact representation for input workloads is generated in a memory system, A memory controller includes firmware (FW) and an encoder including recurrent encoding blocks. Each recurrent encoding block receives one of input commands in an input workload, and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. The last encoding block generates a final hidden state vector as a compact representation vector corresponding to the input commands. The firmware determines a distance function between the compact representation vector and each of multiple compact workload vectors and tunes at least one of firmware parameters based on the determined distances.Type: GrantFiled: March 30, 2021Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventors: Siarhei Zalivaka, Alexander Ivaniuk
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Publication number: 20230045933Abstract: A system which identifies a memory device using a physical unclonable function. The system performs raw read operations on every page of a block; sorts the pages into low and high groups using an average number of ones based on the raw read operations; generates unordered page pairs by sequentially selecting a first page from the low group and a second page from the high group; generates ordered page pairs by selectively converting an order of pages in each pair of the unordered page pairs; and generates a sequence for identifying the selected block based on comparing the average number of ones for pages in each ordered page pair.Type: ApplicationFiled: August 5, 2021Publication date: February 16, 2023Inventors: Siarhei ZALIVAKA, Alexander IVANIUK
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Patent number: 11568093Abstract: Devices, systems and methods for improving reliability and security of a memory system are described. An example method includes receiving a seed value and a data stream, generating, based on the seed and using a physical unclonable function (PUF) generator, a PUF data pattern, generating, based on the seed, a pseudo-random data pattern, performing a first logic operation on the PUF data pattern and the data stream to generate a result of the first logic operation as a first data sequence, and performing a second logic operation on the pseudo-random data pattern and a second data sequence that is based on the first data sequence to generate a result of the second logic operation as a third data sequence for storage on the memory system, wherein the PUF generator is selected at least in-part based on one or more physical characteristics of the memory system.Type: GrantFiled: April 17, 2020Date of Patent: January 31, 2023Assignee: SK hynix Inc.Inventors: Siarhei Zalivaka, Alexander Ivaniuk
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Patent number: 11507573Abstract: The disclosed embodiments provide a system for performing A/B testing of service-level metrics. During operation, the system obtains service-level metrics for service calls made during an A/B test, wherein the service-level metrics are aggregated by user identifiers of multiple users. Next, the system matches the service-level metrics to treatment assignments of the users to a treatment group and a control group in the A/B test. The system then applies the A/B test to a first grouping of the service-level metrics for the treatment group and a second grouping of the service-level metrics for the control group. Finally, the system outputs a result of the A/B test for use in assessing an effect of a treatment variant in the A/B test on the service-level metrics.Type: GrantFiled: September 28, 2018Date of Patent: November 22, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Alexander Ivaniuk, Ruirui Xiang, Ya Xu
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Publication number: 20220326876Abstract: Compact representation for input workloads is generated in a memory system, A memory controller includes firmware (FW) and an encoder including recurrent encoding blocks. Each recurrent encoding block receives one of input commands in an input workload, and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. The last encoding block generates a final hidden state vector as a compact representation vector corresponding to the input commands. The firmware determines a distance function between the compact representation vector and each of multiple compact workload vectors and tunes at least one of firmware parameters based on the determined distances.Type: ApplicationFiled: March 30, 2021Publication date: October 13, 2022Inventors: Siarhei ZALIVAKA, Alexander IVANIUK
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Publication number: 20220303117Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Inventors: Siarhei ZALIVAKA, Alexander IVANIUK
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Publication number: 20220253681Abstract: Compact representation for input workloads is generated in a memory system. The memory system includes a memory device; and a controller including a recurrent neural network coder. The recurrent neural network coder includes an encoder including recurrent encoding blocks. Each recurrent encoding block: receives one of the input commands in an input workload associated with the memory device; and generates a hidden state vector corresponding to the received input command by applying a set of activation functions on the received input command. A last encoding block generates a final hidden state vector as the compact representation vector.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Inventors: Siarhei ZALIVAKA, Alexander IVANIUK
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Patent number: 11394529Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder. It additionally includes a decoding component and a comparator for checking a validity of first and second input data.Type: GrantFiled: January 17, 2020Date of Patent: July 19, 2022Assignee: SK hynix Inc.Inventors: Siarhei Zalivaka, Alexander Ivaniuk
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Publication number: 20210326490Abstract: Devices, systems and methods for improving reliability and security of a memory system are described. An example method includes receiving a seed value and a data stream, generating, based on the seed and using a physical unclonable function (PUF) generator, a PUF data pattern, generating, based on the seed, a pseudo-random data pattern, performing a first logic operation on the PUF data pattern and the data stream to generate a result of the first logic operation as a first data sequence, and performing a second logic operation on the pseudo-random data pattern and a second data sequence that is based on the first data sequence to generate a result of the second logic operation as a third data sequence for storage on the memory system, wherein the PUF generator is selected at least in-part based on one or more physical characteristics of the memory system.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Inventors: Siarhei Zalivaka, Alexander Ivaniuk
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Publication number: 20210303715Abstract: A data scrambler scrambles data for a memory system. The scrambler performs an exclusive OR (XOR) operation on data with a pseudorandom number to generate first scrambled data; identifies a state corresponding to the first scrambled data, among multiple states in a set threshold voltage distribution; transitions the first scrambled data from the identified state to another state in response to a program and erase (PE) counter value; and generates second scrambled data using a subset of encoding values corresponding to the another state, among set encoding values for the multiple states.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Inventors: Siarhei ZALIVAKA, Alexander IVANIUK
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Patent number: 11093382Abstract: Methods and systems are provided for compression and reconstruction of system data. A controller of a memory system includes a compression component for searching for a pattern of an array of system data including a plurality of elements and compressing the array of system data based on the pattern. The array of system data includes neighbor elements corresponding to a first pattern, among the plurality of elements. The compressed system data includes: first information including a first bit indicating a first content; and second information including a first bitmap, each bit of the first bitmap indicating whether a corresponding element is a first element among the neighbor elements of the first pattern.Type: GrantFiled: January 23, 2019Date of Patent: August 17, 2021Assignee: SK hynix Inc.Inventors: Igor Novogran, Alexander Ivaniuk
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Publication number: 20210226772Abstract: A device includes an encoder and a decoder using physically unclonable functions. The encoder includes a first generator for generating a first hash value based on first input data; a first exclusive OR (XOR) operator for performing an XOR operation between second input data and a cryptographic value to generate a first operation value; a second XOR operator for performing an XOR operation between the first hash value and the first operation value to generate a second operation value; a second generator for generating a second hash value based on the first operation value; and an encoding component for encoding the first input data, the second operation value and the second hash value to output first to third encoded data. The decoder contains the same generators and XOR operators as the encoder. It additionally includes a decoding component and a comparator for checking a validity of first and second input data.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Siarhei ZALIVAKA, Alexander IVANIUK
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Publication number: 20210055912Abstract: Multi-level memory cell NAND structure of a memory device is utilized to extract uniqueness from the memory device. Certain unreliable characteristics of NAND-based storage is are used to generate a true random number sequence. A method for generating such sequence is based on physically unclonable function (PUF) which is implemented by extracting unique characteristics of a NAND-based memory device using existing firmware procedures.Type: ApplicationFiled: August 23, 2019Publication date: February 25, 2021Inventors: Siarhei ZALIVAKA, Alexander IVANIUK
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Publication number: 20200410529Abstract: Techniques for generating unbiased estimates of causal effects in online experiments are provided. In one technique, campaign data is received that includes a first set of targeting criteria and a second set of targeting criteria. An online experiment is established that comprises a content delivery campaign that is associated with a treatment group and a control group. Afterward, a content request is received and a first entity that initiated the content request is identified. In response to determining that the first entity is targeted by the campaign based on the first set of targeting criteria, the first entity is randomly assigned to the control group. In responses to second content request, a second entity is identified. In response to determining that the second entity is targeted by the campaign based on the first set of targeting criteria, the second entity is randomly assigned to the treatment group.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Kirill Sergeyevich Lebedev, Mahesh Gupta, Qiongjia Xu, Weishi Zeng, Shaochen Huang, Alexander Ivaniuk, Colin Heinzmann, Justin Marsh, Ruirui Xiang, Elise Georis, Min Liu, Mindaou Gu
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Patent number: 10810060Abstract: Methods and instruction sets are provided for performing event management in an embedded system such as a memory system including a memory device and a controller. The controller divides a group of objects, among a plurality of groups of objects, into a plurality of subgroups, each subgroup including a plurality of objects. The controller counts a number of times that each of the objects is affected by external event using an event counter, updates a count value of each of the subcounters each time an object in the corresponding subgroup is affected by the external event, updates a count value of a main counter each time one of the subcounters reaches a count value equal to a first threshold value; and performing system action on the group of objects, when the count value of the main counter is equal to a second threshold value.Type: GrantFiled: October 26, 2018Date of Patent: October 20, 2020Assignee: SK hynix Inc.Inventors: Igor Novogran, Dzmitryi Kasitsyn, Alexander Ivaniuk
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Publication number: 20200104398Abstract: The disclosed embodiments provide a system for performing unified management of targeting attributes in A/B tests. During operation, the system obtains attribute configurations for attributes to be used in subsequent targeting of users by A/B tests. Next, the system configures, based on the attribute configurations, onboarding of the attributes from an offline environment, a near-real-time environment, and an online environment. During an A/B test, the system retrieves values of one or more of the attributes for a user from locations specified in the attribute configurations. Finally, the system outputs the values with targeting conditions for the A/B test for use in selecting a treatment assignment for the user in the A/B test.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Alexander Ivaniuk, Jingbang Liu, Shaochen Huang, Jiahui Qi, Shaohua Xie