Abstract: A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips.

Abstract: A semiconductor component (1) has a semiconductor chip (5) and a semiconductor component carrier (3) with external connection strips (12, 13, 15). The semiconductor chip (5) has a first electrode (6) and a control electrode (7) on its top side (8) and a second electrode (9) on its rear side (10). The semiconductor chip (5) is fixed by its top side (8) in flip-chip arrangement (11) on a first and a second external connection strip (12, 13) for the first electrode (6) and the control electrode (7). The second electrode (9) is electrically connected to at least one third external connection strip (15) via a bonding tape (14).

Abstract: A power semiconductor component includes at least one power semiconductor chip and surface-mountable external contacts. The power semiconductor chip includes large-area contact areas on its top side and its rear side, which cover essentially the entire top side and rear side, respectively. The top side also includes, alongside the large-area contact area, a small-area contact area; the areal extent of the small-area contact is at least ten times smaller than the areal extent of the large-area contact areas. The small-area contact area is connected to an individual external contact of the power semiconductor component via a bonding wire connection. The large-area contact area of the top side is connected to external contacts via a bonding tape.

Abstract: A power semiconductor component stack, using lead technology with surface-mountable external contacts, includes at least two MOSFET power semiconductor components each having a top side and an underside. The underside includes: a drain external contact area, a source external contact area and a gate external contact area. The top side includes at least one source external contact area and a gate external contact area. The gate external contact areas on the top side and the underside are electrically connected to one another. The power semiconductor component stack is a series circuit or a parallel circuit of MOSFET power semiconductor components arranged one above another in a plastic housing composition.

Abstract: A semiconductor device using lead technology includes a semiconductor chip with external side electrodes of semiconductor components disposed on its top side. On its rear side, the semiconductor chip is connected to a rear side internal lead adapted to the rear side of semiconductor chip. On its top side, the semiconductor chip is connected a plurality of top side internal leads. The top side internal leads are electrically connected to external leads of the semiconductor device.

Abstract: A semiconductor device having surface-mountable external contact areas and a method for producing the same is disclosed. The surface-mountable external contacts are arranged as flat external contacts on the underside of the semiconductor device. In one embodiment, the semiconductor chip of the semiconductor device has a source contact area and a gate contact area on its top side and a drain contact area on its rear side. The source contact area is fixed on a cutout of a heat sink, which is connected to a source external contact, a top side of the heat sink partly forming the top side of the semiconductor device. The drain contact area is electrically connected to a drain external contact and the gate contact area is electrically connected via a connecting element to a gate external contact on the underside of the semiconductor device. Consequently, the semiconductor device as areas which dissipate the heat loss both on the underside and on the top side.

Abstract: A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips.

Abstract: A power semiconductor component stack, using lead technology with surface-mountable external contacts, includes at least two MOSFET power semiconductor components each having a top side and an underside. The underside includes: a drain external contact area, a source external contact area and a gate external contact area. The top side includes at least one source external contact area and a gate external contact area. The gate external contact areas on the top side and the underside are electrically connected to one another. The power semiconductor component stack is a series circuit or a parallel circuit of MOSFET power semiconductor components arranged one above another in a plastic housing composition.

Abstract: A semiconductor component (1) has a semiconductor chip (5) and a semiconductor component carrier (3) with external connection strips (12, 13, 15). The semiconductor chip (5) has a first electrode (6) and a control electrode (7) on its top side (8) and a second electrode (9) on its rear side (10). The semiconductor chip (5) is fixed by its top side (8) in flip-chip arrangement (11) on a first and a second external connection strip (12, 13) for the first electrode (6) and the control electrode (7). The second electrode (9) is electrically connected to at least one third external connection strip (15) via a bonding tape (14).

Abstract: A power semiconductor component includes at least one power semiconductor chip and surface-mountable external contacts. The power semiconductor chip includes large-area contact areas on its top side and its rear side, which cover essentially the entire top side and rear side, respectively. The top side also includes, alongside the large-area contact area, a small-area contact area; the areal extent of the small-area contact is at least ten times smaller than the areal extent of the large-area contact areas. The small-area contact area is connected to an individual external contact of the power semiconductor component via a bonding wire connection. The large-area contact area of the top side is connected to external contacts via a bonding tape.

Abstract: A semiconductor device using lead technology includes a semiconductor chip with external side electrodes of semiconductor components disposed on its top side. On its rear side, the semiconductor chip is connected to a rear side internal lead adapted to the rear side of semiconductor chip. On its top side, the semiconductor chip is connected a plurality of top side internal leads. The top side internal leads are electrically connected to external leads of the semiconductor device.

Abstract: A semiconductor device having surface-mountable external contact areas and a method for producing the same is disclosed. The surface-mountable external contacts are arranged as flat external contacts on the underside of the semiconductor device. In one embodiment, the semiconductor chip of the semiconductor device has a source contact area and a gate contact area on its top side and a drain contact area on its rear side. The source contact area is fixed on a cutout of a heat sink, which is connected to a source external contact, a top side of the heat sink partly forming the top side of the semiconductor device. The drain contact area is electrically connected to a drain external contact and the gate contact area is electrically connected via a connecting element to a gate external contact on the underside of the semiconductor device. Consequently, the semiconductor device as areas which dissipate the heat loss both on the underside and on the top side.