Abstract: Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic.

Abstract: A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.

Abstract: A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain more accurate timing information about the design. However, at an early stage of the design process, the available physical circuit data are often incomplete, not to mention these preliminary data are usually of a lower quality as far as capability of providing an accurate RC delay and capacitance estimation is concerned. To make the best usage of the preliminary data, the present disclosure describes a method of performing a fleeting timing analysis that can be very useful during an early floor planning stage of the design process when there is no opportunity to buffer or widen any exceptionally long interconnect wires within the IC circuit design.