Abstract: Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

Abstract: Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

Abstract: Superconducting circuits and methods for detecting a rising edge of an input signal are described. An example superconducting circuit includes an input terminal for receiving an input signal comprising both positive pulses and negative pulses. The superconducting circuit further includes a first stage, coupled to the input terminal and a first node, configured to suppress both any backward propagating negative pulses and any forward propagating negative pulses, and allow propagation of any forward propagating positive pulses. The superconducting circuit further includes a second stage, coupled to the first node, configured to store a forward propagating positive pulse and reflect a stored positive pulse back to the first node as a negative pulse such that in response to each rising edge of the input signal a return-to-zero signal comprising both a rising edge and a falling edge is provided as an output at the first node.

Abstract: Josephson transmission lines (JTLs) for superconducting devices and related methods are provided. In one example, a device comprising a JTL for propagating quantum pulses in a first direction in response to an application of a clock signal having a plurality of phases is provided. The JTL may include a first inductive element coupled between a first terminal and a second terminal, a first Josephson junction (JJ) coupled between the second terminal and a ground terminal, a second inductive element coupled between the second terminal and a third terminal, and a second JJ coupled between the third terminal and the ground terminal. The second inductive element is configured to form an inductive loop, and the inductive loop may be configured to operate in a mode such that a quantum pulse cannot travel in a second direction opposite from the first direction regardless of a phase of the clock signal.

Abstract: Superconducting circuits and methods for detecting a rising edge of an input signal are described. An example superconducting circuit includes an input terminal for receiving an input signal comprising both positive pulses and negative pulses. The superconducting circuit further includes a first stage, coupled to the input terminal and a first node, configured to suppress both any backward propagating negative pulses and any forward propagating negative pulses, and allow propagation of any forward propagating positive pulses. The superconducting circuit further includes a second stage, coupled to the first node, configured to store a forward propagating positive pulse and reflect a stored positive pulse back to the first node as a negative pulse such that in response to each rising edge of the input signal a return-to-zero signal comprising both a rising edge and a falling edge is provided as an output at the first node.

Abstract: Superconducting circuits and methods for latching data are described. An example superconducting circuit includes an edge detect circuit configured to receive a logical clock signal and generate a return-to-zero clock signal. The superconducting circuit further includes a first latch configured to receive the logical clock signal and an input data signal, where the first latch is further configured to selectively delay the input data signal to generate a delayed data signal. The superconducting circuit further includes a second latch configured to receive the return-to-zero clock signal and the delayed data signal, where the second latch is further configured to capture a logical high value corresponding to the input data signal in response to a rising edge of the return-to-zero clock signal and capture a low logical value corresponding to the input data signal in response to a falling edge of the return-to-zero clock signal.

Abstract: Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.

Abstract: Superconducting circuits-based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a circuit for an A-and-not-B gate including an output terminal, a first input terminal for receiving a first set of single flux quantum (SFQ) pulses, and a second input terminal for receiving a second set of SFQ pulses is provided. The circuit further includes a first Josephson junction (JJ) coupled to receive the first set of SFQ pulses. The circuit further includes a second JJ, where the second JJ when positively biased is configured to negatively bias the first JJ such that the circuit is configured to not pass the first set of SFQ pulses to the output terminal only when the second set of SFQ pulses have arrived at the second input terminal prior to an arrival of the first set of SFQ pulses at the first input terminal.

Abstract: Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.

Abstract: Superconducting circuits-based devices and methods for an A-and-not-B gate are provided. In one example, a circuit for an A-and-not-B gate including an output terminal, a first input terminal for receiving a first set of single flux quantum (SFQ) pulses, and a second input terminal for receiving a second set of SFQ pulses is provided. The circuit may further include a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result. The circuit may further include a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal and provide an output via the output terminal.

Abstract: Josephson transmission lines (JTLs) for superconducting devices and related methods are provided. In one example, a device comprising a JTL for propagating quantum pulses in a first direction in response to an application of a clock signal having a plurality of phases is provided. The JTL may include a first inductive element coupled between a first terminal and a second terminal, a first Josephson junction (JJ) coupled between the second terminal and a ground terminal, a second inductive element coupled between the second terminal and a third terminal, and a second JJ coupled between the third terminal and the ground terminal. The second inductive element is configured to form an inductive loop, and the inductive loop may be configured to operate in a mode such that a quantum pulse cannot travel in a second direction opposite from the first direction regardless of a phase of the clock signal.

Abstract: A tri-stable storage loop useful in reciprocal quantum logic (RQL) gate circuits and systems has control and signal input lines. When alternating stable current storage states are induced in the storage loop by an alternating input provided to the control input line, provision of a positive SFQ pulse on the signal input line while the storage loop stores a positive current changes the storage loop from alternating between a positive-current state and a null-current state to alternating between a negative-current state and the null-current state, and provision of a negative SFQ pulse on the signal input line while the storage loop stores a negative current changes the storage loop from alternating between the negative-current state and the null-current state to alternating between the positive-current state and the null-current state.

Abstract: Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direction and a second JTL for propagating a second set of quantum signals in the first direction is provided. The device may include a logic gate having a first input terminal for receiving the first set of quantum signals via the first JTL, and a second input terminal. The device may include a unidirectional buffer having a first input terminal for receiving the second set of quantum signals via the second JTL and an output terminal for coupling the second set of quantum signals to the second input terminal of the logic gate, where the unidirectional buffer may be configured to propagate quantum signals in only the first direction.

Abstract: An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

Abstract: An reciprocal quantum logic (RQL) gate circuit has an input stage having logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and an amplifying output stage comprising a JTL to deliver an output signal. The input stage includes two or more storage loops, at least two being associated each with a logical input, each comprising an input Josephson junction (JJ), a storage inductor, and a logical decision JJ, the logical decision JJ being common to all the storage loops associated with the logical inputs and being configured to trigger based on biasing provided by one or more currents stored in the storage loops and a bias signal provided to the circuit. The output stage asserts an output based on the triggering of the logical decision JJ.

Abstract: Superconducting devices with enforced directionality and related methods are provided. In one example, a device including a first Josephson junction transmission line (JTL) for propagating a first set of quantum signals in a first direction and a second JTL for propagating a second set of quantum signals in the first direction is provided. The device may include a logic gate having a first input terminal for receiving the first set of quantum signals via the first JTL, and a second input terminal. The device may include a unidirectional buffer having a first input terminal for receiving the second set of quantum signals via the second JTL and an output terminal for coupling the second set of quantum signals to the second input terminal of the logic gate, where the unidirectional buffer may be configured to propagate quantum signals in only the first direction.