Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Technology is disclosed for a computing system with a printed circuit board having a top and bottom; an integrated circuit component coupled to the top of the board; a passive heat exchanger coupled to the top of the board and spaced from the integrated circuit component; at least one electronic component coupled to the printed circuit board below the top of the printed circuit board; and at least one heat pipe having an evaporator end adjacent the electronic component and extending away from the evaporator end along the bottom of the board to a condenser end above the top of the board, the condenser end being thermally coupled to the passive heat exchanger on the top of the board; wherein heat from electronic component is moved away from the electronic component and the integrated circuit component to the passive heat exchanger.

Abstract: Various embodiments provide a voltage regulator circuit including two or more discontinuous conduction mode (DCM) phases coupled to an output node and coupled in parallel with one another. A control circuit may detect a trigger and switch all of the two or more DCM phases to a first state (charge state) responsive to the detection. The control circuit may switch a first DCM phase, of the two or more DCM phases, to a second state (discharge state) after a first predetermined time period in the first state and may switch a second DCM phase, of the two or more DCM phases, to the second state after a second predetermined time period in the first state, wherein the second predetermined time period is different than the first predetermined time period. Other embodiments may be described and claimed.

Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

Abstract: A microelectronic assembly is provided, comprising a first IC die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR) electrically coupled to the first IC die, a package substrate having inductors of the VR electrically coupled to the first IC die and the second IC die, and a mold compound between the first IC die and the package substrate. The VR receives power at a first voltage from the package substrate and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the second IC die is in the mold compound. In some embodiments, the mold compound and the second IC die are comprised in a discrete interposer electrically coupled to the first IC die with die-to-die interconnects and to the package substrate with die-to-package substrate interconnects.

Abstract: A microelectronic assembly is disclosed, comprising a first integrated circuit (IC) die having electrical load circuits, first control circuits, and a second control circuit, a second IC die having powertrain (PTR) phase circuits electrically coupled to the first IC die, and inductors in a package substrate electrically coupled to the first IC die and the second IC die within a package. Individual ones of the first control circuits regulates power to a corresponding one of the electrical load circuits. The second control circuit maps the first control circuits and the PTR phase circuits. The PTR phase circuits control power to the inductors. The first control circuits, the second control circuit, the PTR phase circuits and the inductors together function as a voltage regulator configured to receive power from the package substrate at a first voltage and deliver power to the electrical load circuits at a second voltage.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Embodiments herein relate to a circuit which generates a sawtooth waveform based on an adaptive feedback loop that self-corrects the ramp up rate to account for variations in a device. The sawtooth waveform is obtained by repeatedly charging and discharging a capacitor according to a clock signal. The sawtooth waveform can be sampled once per clock period at a comparator which provides a corresponding binary output to a state machine. If the binary output indicates the amplitude of the sawtooth waveform is below a desired maximum voltage, the state machine outputs a code word to a digitally-controlled variable current source to increase the output current. The sawtooth waveform can be used to provide a pulse-width modulated (PWM) waveform such as for a DC-DC converter.

Abstract: Embodiments herein relate to identifying, by phase current balancing (PCB) circuitry, an indication of whether a measured current of a pulse-width modulated (PWM) signal of a plurality of PWM signals is greater than or less than an average current of the plurality of PWM signals. Embodiments further relate to adjusting, by the PCB circuitry, a bias-value of a non-modulated edge of a duty cycle of the PWM signal. Other embodiments may be described and claimed.

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc.

Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Abstract: Various embodiments provide a voltage regulator circuit including two or more discontinuous conduction mode (DCM) phases coupled to an output node and coupled in parallel with one another. A control circuit may detect a trigger and switch all of the two or more DCM phases to a first state (charge state) responsive to the detection. The control circuit may switch a first DCM phase, of the two or more DCM phases, to a second state (discharge state) after a first predetermined time period in the first state and may switch a second DCM phase, of the two or more DCM phases, to the second state after a second predetermined time period in the first state, wherein the second predetermined time period is different than the first predetermined time period. Other embodiments may be described and claimed.

Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

Abstract: Various embodiments provide a voltage regulator circuit including two or more discontinuous conduction mode (DCM) phases coupled to an output node and coupled in parallel with one another. A control circuit may detect a trigger and switch all of the two or more DCM phases to a first state (charge state) responsive to the detection. The control circuit may switch a first DCM phase, of the two or more DCM phases, to a second state (discharge state) after a first predetermined time period in the first state and may switch a second DCM phase, of the two or more DCM phases, to the second state after a second predetermined time period in the first state, wherein the second predetermined time period is different than the first predetermined time period. Other embodiments may be described and claimed.

Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Abstract: Various embodiments provide a voltage regulator circuit including two or more discontinuous conduction mode (DCM) phases coupled to an output node and coupled in parallel with one another. A control circuit may detect a trigger and switch all of the two or more DCM phases to a first state (charge state) responsive to the detection. The control circuit may switch a first DCM phase, of the two or more DCM phases, to a second state (discharge state) after a first predetermined time period in the first state and may switch a second DCM phase, of the two or more DCM phases, to the second state after a second predetermined time period in the first state, wherein the second predetermined time period is different than the first predetermined time period. Other embodiments may be described and claimed.