Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces withIn the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisoropically wet etching the trench to expand the trench.

Abstract: A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention is disclosed and claimed. The method includes the steps of providing a semiconductor wafer, depositing a valve metal on the wafer, placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the valve metal to form a metal oxide when a potential difference is provided between the valve metal and the solution and processing the wafer using the metal oxide layer.

Abstract: A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.

Abstract: A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Abstract: A method for depositing a sacrificial oxide for fabricating a semiconductor device includes preparing p-doped silicon regions on a semiconductor wafer for depositing a sacrificial oxide on the p-doped silicon regions. The method also includes the step of placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the p-doped silicon regions to form a sacrificial oxide on the p-doped silicon regions when a potential difference is provided between the wafer and the solution. Processing the wafer using the sacrificial oxide layer is also included.

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.

Abstract: A method of forming semiconductor devices in accordance with the present invention includes the steps of providing a deep trench in a substrate, the deep trench having a lower portion and forming a dielectric layer in the deep trench by lining the lower portion of the deep trench with a dielectric layer, the dielectric layer including titanium. A semiconductor device includes a substrate having a trench formed therein, a storage node formed in the trench and capacitively coupled to the substrate and a dielectric layer formed in the trench between the storage node and the substrate, the dielectric layer lining a lower portion of the trench wherein the dielectric layer includes titanium oxide.

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

Abstract: In accordance with the present invention, a method for etching back filler material for a buried strap for deep trench capacitors includes the steps of forming a trench in a substrate, filling the trench with a first filler material, recessing the first filler material to a predetermined depth relative to a dielectric collar formed in the trench, forming a divot by etching back the dielectric collar, depositing a liner over the first filler material and portions of the substrate exposed by the formation of the trench, and depositing a second filler material on the liner. A surface of the second filler material is prepared by etching the surface with a wet etchant to provide a hydrogen terminated silicon surface. Wet etching the second filler material is performed to etch back the second filler material selective to the liner and the substrate. The second filler material is etched to form a buried strap.

Abstract: A system for measuring surface features having form birefringence in accordance with the present invention includes a radiation source for providing radiation incident on a surface having surface features. A radiation detecting device is provided for measuring characteristics of the incident radiation after being reflected from the surface features. A rotating stage rotates the surface such that incident light is directed at different angles due to the rotation of the rotating stage. A processor is included for processing the measured characteristics of the reflected light and correlating the characteristics to measure the surface features.

Abstract: Methods and apparatus for evaluating internal film stress on a sample at high lateral resolutions are provided. The sample comprises at least one material and has a planar or smooth surface. To determine internal stress, a calibration curve correlating a set of first ellipsometric parameter amplitudes to a set of first stress values is generated. One first stress value is correlated to one first ellipsometric amplitude. Then, the sample for which stress is to be determined is rotated as a function of sample rotation angle a and is measured for a set of second ellipsometric parameter at a selected area of the sample to determine a second ellipsometric amplitude. The internal stress at the selected area of the sample is then determined from the calibration curve by using the second ellipsometric amplitude as an index to determine a corresponding stress value from the calibration curve.