Abstract: In one embodiment, a method includes receiving a request from a remote distributed fabric protocol (DFP) system master, using a dedicated processor of a DFP system member, to register local I2C devices on the DFP system member, and sending an acknowledgement including a list of local I2C bus devices back to the DFP system master using the dedicated processor of the DFP system member. The acknowledgement present on the DFP system member. In another embodiment, a system includes a local processor, one or more local I2C bus devices, and a dedicated processor electrically coupled to the local I2C bus devices. The dedicated processor is configured to route interrupts from the local I2C bus devices to the local processor, and expose the local I2C devices to a remote DFP system master by sending details of the local I2C bus devices to the remote DFP system master.

Abstract: A clustered network may include a plurality of switch boxes where a master switch box may communicate and control hardware devices in remote switch boxes. The switch boxes in the network may each include a multiplexer, for example, a field programmable array (FPGA) that may process message requests related to hardware devices of a switch box. If the hardware device is in a remote switch box, then the FPGA of the master switch box may process the status data from the remote switch box so that a local processor in the master switch box can read the status data.

Abstract: According to one embodiment, a method includes performing functionality of a management plane and a control plane for a switch system using a processor of an external host coupled to the switch system via one or more peripheral component interconnect express (PCIe) ports. The method also includes providing a direct memory access (DMA) facility between the external host and switching logic of the switch system. The switch system includes a PCIe interface block coupled to PCIe ports configured to couple to external PCIe devices. Also, the PCIe interface block includes logic configured to provide DMA for each PCIe lane thereof. The switch system also includes multiple switched Ethernet ports configured to couple to one or more external Ethernet devices and switching logic configured to switch between the multiple switched Ethernet ports and the PCIe ports using DMA and a local processor coupled to the PCIe interface block.

Abstract: In one embodiment, a method includes sending a request to one or more distributed fabric protocol (DFP) system members in order to retrieve one or more events from the one or more DFP system members, receiving one or more acknowledgements to the request from the one or more DFP system members at a local network switch of a DFP system master, upon receipt of at least one packet in which the one or more events are encapsulated as data: decoding the at least one packet to retrieve details of the one or more events using a dedicated processor of the DFP system master, creating and sending a message signaled interrupt (MSI) comprising the details of the one or more events to a local processor of the DFP system master using the dedicated processor, and reading the MSI using the local processor of the DFP system master.

Abstract: According to one embodiment, a method includes performing functionality of a management plane and a control plane for a switch system using a processor of an external host coupled to the switch system via one or more peripheral component interconnect express (PCIe) ports. The method also includes providing a direct memory access (DMA) facility between the external host and switching logic of the switch system. The switch system includes a PCIe interface block coupled to PCIe ports configured to couple to external PCIe devices. Also, the PCIe interface block includes logic configured to provide DMA for each PCIe lane thereof. The switch system also includes multiple switched Ethernet ports configured to couple to one or more external Ethernet devices and switching logic configured to switch between the multiple switched Ethernet ports and the PCIe ports using DMA and a local processor coupled to the PCIe interface block.

Abstract: In one embodiment, a method includes receiving a request from a remote distributed fabric protocol (DFP) system master, using a dedicated processor of a DFP system member, to register local I2C devices on the DFP system member, and sending an acknowledgement including a list of local I2C bus devices back to the DFP system master using the dedicated processor of the DFP system member. The acknowledgement present on the DFP system member. In another embodiment, a system includes a local processor, one or more local I2C bus devices, and a dedicated processor electrically coupled to the local I2C bus devices. The dedicated processor is configured to route interrupts from the local I2C bus devices to the local processor, and expose the local I2C devices to a remote DFP system master by sending details of the local I2C bus devices to the remote DFP system master.

Abstract: According to one embodiment, a switch system includes an external host connected via a peripheral component interconnect express (PCIe) port to a switch system, the external host being configured to perform functionality of a management plane and a control plane for the switch system, the external host having a processor. In another embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code including computer readable program code configured to perform functionality of a management plane and a control plane for a switch system using a processor of an external host. Other systems, computer program products, and methods are described according to more embodiments.

Abstract: In one embodiment, a method includes accessing every local I2C bus device, using a local processor of a distributed fabric protocol (DFP) system member, to ascertain which local I2C bus devices are present, receiving a request from a remote DFP system master, using a dedicated processor of the DFP system member, to register local I2C devices on the DFP system member in order to allow the DFP system master to have access to the local I2C devices, sending an acknowledgement to the request back to the DFP system master, receiving a read request from the DFP system master to read the local I2C bus devices and authenticating the read request, encapsulating details of the local I2C bus devices into a packet similar to that in which the read request was received, and sending the packet to a local network switch to be switched to the DFP system master.

Abstract: In one embodiment, a switch includes a processor and logic integrated with and/or executable by the processor, the logic being configured to cause the processor to receive a packet at an ingress port of the switch, forward the packet to a buffered switch when at least one congestion condition is met, where the buffered switch is configured to evaluate congestion conditions of a fabric network, and forward the packet to a low-latency switch when the at least one congestion condition is not met, where the low-latency switch includes an additional policy table provided with forwarding decisions based on the congestion conditions of the fabric network. Other switches, systems, methods, and computer program products for providing low latency packet forwarding with guaranteed delivery are described according to more embodiments.

Abstract: A differential transmission line with a common mode notch filter includes adjacently arranged, repeating differential transmission line pair sections. The sections have lengths that are each equal to half of an electric wavelength of a lowest frequency of a common mode electromagnetic wave to be suppressed during transmission of an electric signal over the differential transmission line. Each section includes a pair of conductors separated from one another by a spacing. The width of each conductor and the spacing between the conductors of each section vary over the length thereof according to a same pattern such that at every point over the length of each section a differential mode impedance of the differential transmission line is identical. A common mode impedance of the differential transmission line changes periodically in accordance with the lengths of the sections.

Abstract: In one embodiment, a switch includes a processor and logic integrated with and/or executable by the processor, the logic being configured to cause the processor to receive a packet at an ingress port of the switch, forward the packet to a buffered switch when at least one congestion condition is met, where the buffered switch is configured to evaluate congestion conditions of a fabric network, and forward the packet to a low-latency switch when the at least one congestion condition is not met, where the low-latency switch includes an additional policy table provided with forwarding decisions based on the congestion conditions of the fabric network. Other switches, systems, methods, and computer program products for providing low latency packet forwarding with guaranteed delivery are described according to more embodiments.

Abstract: The present invention proposes methods and structures for designing electronic circuit elements for frequency suppression of electromagnetic waves using a transmission line grating. The method includes determining a frequency to be suppressed. Using the electrical wavelength of the frequency to be suppressed, determine a length of a plurality of equal length sections of the differential transmission lines is determined. Using the frequency to be suppressed and the electronic circuit requirements, determine a set of properties for the plurality of equal length sections of the differential transmission lines. The transmission line grating is created using a plurality of alternating equal length sections of the differential transmission lines.

Abstract: In one embodiment, a method includes accessing every local I2C bus device, using a local processor of a distributed fabric protocol (DFP) system member, to ascertain which local I2C bus devices are present, receiving a request from a remote DFP system master, using a dedicated processor of the DFP system member, to register local I2C devices on the DFP system member in order to allow the DFP system master to have access to the local I2C devices, sending an acknowledgement to the request back to the DFP system master, receiving a read request from the DFP system master to read the local I2C bus devices and authenticating the read request, encapsulating details of the local I2C bus devices into a packet similar to that in which the read request was received, and sending the packet to a local network switch to be switched to the DFP system master.

Abstract: In one embodiment, a method includes sending a request to one or more distributed fabric protocol (DFP) system members in order to retrieve one or more events from the one or more DFP system members, receiving one or more acknowledgements to the request from the one or more DFP system members at a local network switch of a DFP system master, upon receipt of at least one packet in which the one or more events are encapsulated as data: decoding the at least one packet to retrieve details of the one or more events using a dedicated processor of the DFP system master, creating and sending a message signaled interrupt (MSI) comprising the details of the one or more events to a local processor of the DFP system master using the dedicated processor, and reading the MSI using the local processor of the DFP system master.

Abstract: In one embodiment, a system includes a switch configured for communicating with a low-latency switch and a buffered switch, the switch having a processor adapted for executing logic, logic adapted for receiving a packet at an ingress port of a switch, logic adapted for receiving congestion information, logic adapted for determining that at least one congestion condition is net based on at least the congestion information, logic adapted for applying a packet forwarding policy to the packet when the at least one congestion condition is met, logic adapted for forwarding the packet to a buffered switch when the packet satisfies the packet forwarding policy, and logic adapted for forwarding the packet to a low-latency switch when the at least one congestion condition is not met.

Abstract: In one embodiment, a system includes a local processor, a peripheral component interconnect express (PCIe) switch electrically coupled to the local processor, one or more local I2C bus devices, a dedicated processor electrically coupled to the one or more local I2C bus devices and the PCIe switch, and a local network switch electrically coupled to the dedicated processor and the PCIe switch, wherein the dedicated processor is adapted for routing interrupts from the one or more local I2C bus devices to the local processor, and wherein the local processor is adapted for handling the interrupts from the one or more local I2C bus devices. Other distributed fabric protocol (DFP) systems, computer program products, and methods are presented according to additional embodiments.

Abstract: In one embodiment, a method includes sending a request to one or more distributed fabric protocol (DFP) system members in order to retrieve one or more events from the one or more DFP system members, wherein the one or more events are received as data encapsulated in a packet(s), receiving one or more acknowledgements to the request from the one or more DFP system members at a local network switch of the DFP system master, upon receipt of the at least one packet: decoding the at least one packet to retrieve details of the one or more events using a dedicated processor of the DFP system master, creating and sending a message signaled interrupt (MSI) comprising the details of the one or more events to a local processor of the DFP system master using the dedicated processor, and reading the MSI using the local processor of the DFP system master.

Abstract: Embodiments of the invention relate to scaled-out and distributed network packet processors and switch central cores. One embodiment relates to a system including multiple central core processing devices, wherein each central core processing device includes: a virtual central core interface for establishing scaled-out and distributed virtual communication connections with the central core processing devices and a packet processor interface manager connected with multiple packet processing interfaces. Multiple packet processors each include: a packet processor thread manager for managing and processing packets received by central core processing devices and multiple central core processing interfaces for providing connectivity between the packet processors and the plurality of central core processing devices. The packet processing interfaces and the central core processing interfaces provide scaled-out and distributed connectivity of the packet processors to one or more central core processing devices.

Abstract: According to one embodiment, a switch system includes an external host connected via a peripheral component interconnect express (PCIe) port to a switch system, the external host being configured to perform functionality of a management plane and a control plane for the switch system, the external host having a processor. In another embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code including computer readable program code configured to perform functionality of a management plane and a control plane for a switch system using a processor of an external host. Other systems, computer program products, and methods are described according to more embodiments.

Abstract: Embodiments of the invention relate to scaled-out and distributed network packet processors and switch central cores. One embodiment relates to a system including multiple central core processing devices, wherein each central core processing device includes: a virtual central core interface for establishing scaled-out and distributed virtual communication connections with the central core processing devices and a packet processor interface manager connected with multiple packet processing interfaces. Multiple packet processors each include: a packet processor thread manager for managing and processing packets received by central core processing devices and multiple central core processing interfaces for providing connectivity between the packet processors and the plurality of central core processing devices. The packet processing interfaces and the central core processing interfaces provide scaled-out and distributed connectivity of the packet processors to one or more central core processing devices.