Abstract: A power system for controlling power to low voltage CMOS circuits. The power system can be used in circuits having a low voltage supply and a high voltage supply, wherein the low voltage supply powers low voltage circuit components and the high voltage supply powers high voltage circuit components. The power system comprises a first switch coupled between the low voltage supply and the low voltage circuit components, a second switch coupled between the low voltage circuit components and a circuit ground, and a power control circuit coupled to the high voltage supply and the circuit ground and having a control output coupled to the first and second switches, wherein when the control output is in a first state the low voltage supply and the circuit ground are connected to the low voltage circuit components and when the control output is in a second state the low voltage supply and the circuit ground are disconnected from the low voltage circuit components.

Abstract: A data transfer arrangement. The data transfer arrangement includes two active pull up/active pull down bus drivers and a voltage precharge source. A differential bus is coupled to the bus drivers and to the voltage precharge source. A latching sense amplifier is coupled to the differential bus and serves as the bus receiver. The bus drivers operate in a precharge phase and a data transfer phase. The bus receiver operates in an analogous but opposite manner, i.e., when the bus drivers are in the precharge phase, the bus receiver is in the data transfer phase and when the bus drivers are in the data transfer phase, the bus receiver is in a precharge phase.

Abstract: A pipelined domino architecture includes pairs of pipeline stages each comprising a first active clocked stage and a number of subsequent self-reset logic gates. Each pipeline stage is clocked by one or the other of a clock signal. Each active clocked stage and self-reset logic gate of any particular pipeline state includes a reset circuit to reset the output of such stage or gate at the conclusion of an evaluation period that is initiated by a phase of the clock signal. Only the active clocked stage is clocked; the self-reset logic stages rely upon the reset of the output of the active clocked stage to generate the necessary reset signals that will reset their respective outputs.

Abstract: A system for increasing the speed and noise immunity of signals transmitted in low voltage CMOS applications. The system includes a transmission device for transmitting a signal in a CMOS circuit, wherein the CMOS circuit includes a high voltage power supply and a low voltage power supply and the signal is transmitted between first and second portions of the CMOS circuit that are coupled to the low voltage power supply.

Abstract: An apparatus for adjusting static thresholds of CMOS circuits. The apparatus includes a low reference circuit including at least one channel n-channel MOS device having a back gate and a high reference circuit including at least one p-channel MOS device having a back gate. A feedback loop is provided for providing a control voltage to the back gate of the n-channel NMOS device while a second feedback loop is provided for providing a second control voltage to the back gate of the p-channel MOS device. A control voltage is applied to the first feedback loop while a control voltage is applied to the second feedback loop. The output of the low reference circuit is coupled to the first feedback loop and the output of the high reference circuit is coupled to the second feedback loop.

Abstract: A mulitport register file including a memory cell array having a plurality of addressable memory locations and N bit lines associated with each memory cell in the memory cell array, wherein there are N port inputs to each addressable location in the memory cell array and at most N/2+1 word lines associated with each addressable memory location. A plurality of select and priority circuits having N port inputs and at most N/2+1 outputs, the outputs of a separate select and priority circuit connected to the word lines associated with each of the addressable memory locations to select a single bit line associated with each memory location corresponding to the port input with the highest priority when more than one port input at the same addressable memory location carries an address select signal. Read address comparators and a data transfer unit operate to ensure that the data from the memory cells is also output to sense amplifiers corresponding to the non-selected lower priority port inputs.