Patents by Inventor Alexander Viktorovich Bolotnikov
Alexander Viktorovich Bolotnikov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014328Abstract: In some aspects, the techniques described herein relate to a diode including: a substrate of a first conductivity type; a semiconductor layer of the first conductivity type disposed on the substrate, the semiconductor layer including a drift region; a shield region of a second conductivity type disposed in the semiconductor layer adjacent to the drift region; a surface region of the first conductivity type disposed in a first portion of the drift region adjacent to the shield region, the surface region having a doping concentration that is greater than a doping concentration of a second portion of the drift region adjacent to the surface region, the second portion of the drift region excluding the surface region; and a Schottky material disposed on: at least a portion of the shield region; the surface region in the first portion of the drift region; and the second portion of the drift region.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Alexander Viktorovich BOLOTNIKOV, Fredrik ALLERSTAM
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Publication number: 20230395730Abstract: In some aspects, a diode can include: a substrate and semiconductor layer of a first conductivity type, the semiconductor layer being disposed on the substrate and including a drift region; a shield region of a second conductivity type disposed in the semiconductor layer adjacent to the drift region; a first Schottky material disposed on at least a portion of the shield region and on a first portion of the drift region, the first Schottky material defining a first Schottky contact with an upper portion of the drift region; and a second Schottky material disposed on a second portion of the drift region, the second Schottky material being adjacent to the first Schottky material, the second Schottky material defining a second Schottky contact with the upper portion of the drift region, the first Schottky contact having a barrier height that is less than a barrier height of the second Schottky contact.Type: ApplicationFiled: June 7, 2022Publication date: December 7, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Alexander Viktorovich BOLOTNIKOV
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Patent number: 11764257Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: January 10, 2022Date of Patent: September 19, 2023Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20220130953Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11271076Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: GrantFiled: July 19, 2019Date of Patent: March 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11245003Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: July 19, 2019Date of Patent: February 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11233157Abstract: A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.Type: GrantFiled: September 28, 2018Date of Patent: January 25, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20210288180Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 11069772Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.Type: GrantFiled: December 14, 2018Date of Patent: July 20, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 11063115Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.Type: GrantFiled: December 9, 2019Date of Patent: July 13, 2021Assignee: General Electric CompanyInventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Yang Sui
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Patent number: 11056586Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.Type: GrantFiled: September 28, 2018Date of Patent: July 6, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Reza Ghandi, David Alan Lilienfeld, Peter Almem Losee
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Patent number: 11031472Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.Type: GrantFiled: February 21, 2019Date of Patent: June 8, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Peter Almern Losee, Reza Ghandi, Alexander Viktorovich Bolotnikov
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Patent number: 10957759Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.Type: GrantFiled: December 28, 2018Date of Patent: March 23, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Patent number: 10937870Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).Type: GrantFiled: February 12, 2020Date of Patent: March 2, 2021Assignee: General Electric CompanyInventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
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Publication number: 20200258985Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).Type: ApplicationFiled: February 12, 2020Publication date: August 13, 2020Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
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Publication number: 20200212182Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.Type: ApplicationFiled: February 21, 2019Publication date: July 2, 2020Inventors: Peter Almern Losee, Reza Ghandi, Alexander Viktorovich Bolotnikov
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Publication number: 20200203476Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20200203477Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20200203487Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.Type: ApplicationFiled: December 28, 2018Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
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Publication number: 20200194546Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Inventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee