Abstract: This invention is a novel high-speed neural network based processor for solving the "traveling salesman" and other global optimization problems. It comprises a novel hybrid architecture employing a binary synaptic array whose embodiment incorporates the fixed rules of the problem, such as the number of cities to be visited. The array is prompted by analog voltages representing variables such as distances. The processor incorporates two interconnected feedback networks, each of which solves part of the problem independently and simultaneously, yet which exchange information dynamically.

Abstract: An electrically programmable, erasable, read-only memory is comprised of an array of vertical porous floating gate MOSFET structures in a layer of a-Si with parallel X and parallel Y conductors on opposite sides of the a-Si layer functioning as source and drain electrodes. The floating gate of each vertical MOSFET structure consists of a plurality of electrically insulated metallic particles embedded in the a-Si layer between said source and said drain electrodes with the metallic particles adjacent to the source electrodes. The insulation between the metallic particles and the a-Si material is thick enough to prevent tunneling of electrons but the insulation between the particles and the source electrode is thinner to allow tunneling of electrons at a predetermined threshold voltage to store a charge in the porous floating gate. Alternatively, the metal particles may be gathered into one insulated toroidal gate which controls current through a-Si in the center of the toroidal gate.

Abstract: A multi-layered, thin-film, digital memory having associative recall. There is a first memory matrix and a second memory matrix.

Abstract: Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.