Abstract: A fan out buildup substrate stackable package includes an electronic component having an active surface having bond pads. A package body encloses the electronic component. A first die side buildup dielectric layer is applied to the active surface of the electronic component and to a first surface of the package body. A first die side circuit pattern is formed on the first die side buildup dielectric layer and electrically connected to the bond pads. Through vias extend through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern. The fan out buildup substrate stackable package is extremely thin and provides a high density interconnect on both sides of the package allowing additional devices to be stacked thereon.

Abstract: A stacked inverted flip chip package includes a substrate having a secondary electronic component opening and first traces. Primary flip chip bumps electrically and physically couple a primary electronic component structure to the substrate. Secondary flip chip bumps electrically and physically couple an inverted secondary electronic component to the primary electronic component structure between the primary electronic component structure and the substrate and within the secondary electronic component opening. By placing the secondary electronic component between the primary electronic component structure and the substrate, the height of the stacked inverted flip chip package is minimized.